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S3C6400X RISC MICROPROCESSOR
XnRESET cannot be masked and is always enabled. Upon assertion of XnRESET, S3C6400X enters into reset
state regardless of the previous mode. XnRSET must be held long enough to allow internal stabilization and
propagation of the reset state to enter proper reset state.
Power regulator for S3C6400X must be stable prior to the deassertion of XnRESET. Otherwise, it may damage
S3C6400X and the operation is unpredictable.
Warm reset
Warm reset is invoked when XnWRESET pin is asserted for more 100ns in NORMAL, IDLE, and STOP modes. In
SLEEP mode, it is treated as a wake-up event. XnWRESET is ignored if XnBATFLT holds low or if the system is
in wake-up period. As shown in Table 3-5, all registers except SYSCON, RTC, and GPIO are initialized.
During the warm reset, the following actions occur:
All blocks except for ALIVE and RTC block go to their pre-defined reset state.
All pins get their reset state.
The nRSTOUT pin is asserted during watchdog reset.
When XnWRESET signal is asserted as '0', the following sequence occurs:
1. SYSCON requests AHB bus controller to finish current AHB bus transactions.
2. AHB bus controllers send acknowledges to SYSCON after current bus transactions are finished.
3. SYSCON request DOMAIN-V to finish current AXI-bus transaction.
4. AXI bus controller sends acknowledge to SYSCON after the current bus transaction is finished.
5. SYSCON requests external memory controllers to enter into self-refresh mode, since the contents in the
external memory must be preserved while warm reset is asserted.
6. The memory controller's sends acknowledgement when they are in self-refresh mode.
7. SYSCON assert internal reset signals and XnRSTOUT.
Software reset
Software reset is invoked when a software write 0x6400 to SW_RST. The behavior is same as warm reset case.
Watchdog reset
Watchdog reset is invoked when a software hang-up. Then, the software cannot initialize a register within WDT
and WDT makes time-out signals for watchdog reset. During the watchdog reset, the following actions take place:
All blocks except for ALIVE and RTC block go to their pre-defined reset state.
All pins get their reset state.
The nRSTOUT pin is asserted during watchdog reset.
Watchdog reset can be activated in NORMAL and IDLE mode, since WDT can generate time-out signal. It is
invoked when watchdog timer and reset are enabled. Then, the following sequence takes place:
1. WDT generate time-out signal.
2. SYSCON invokes reset signals and initialize internal IPs.
3. The reset including nRSTOUT will be asserted until the reset counter, RST_STABLE, is expired.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SYSTEM CONTROLLER
3-17
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