Samsung S5PC110 Manual

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Rev. 0.0, Jan.2009

S5PC110

RISC Microprocessor

Revision 1.00

February 2010

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Summary of Contents for Samsung S5PC110

Page 2: Important Notice
Samsung products are not designed, intended, or use of the information contained herein. authorized for use as components in systems intended Samsung reserves the right to make changes in its for surgical implant into the body, for other products or product specifications with the intent to...
Page 3: Revision History
Rev. 0.0, Jan.2009 Revision History Revision No. Date Description Author(s) 0.00 February 27, 2010 - Initial draft S.H Yoon...
Page 4 Section 1 OVERVIEW...
Page 5: Table Of Contents
Table of Contents Overview of S5PC110.................1-1 1.1 Architectural Overview ..........................1-1 1.2 Block Diagram of S5PC110 ........................1-2 1.3 Key Features of S5PC110 ........................1-3 1.3.1 Microprocessor ..........................1-4 1.3.2 Memory Subsystem .......................... 1-5 1.3.3 Multimedia ............................1-6 1.3.4 Audio Subsystem..........................1-9 1.3.5 Security Subsystem ..........................
Page 6 List of Figures Figure Title Page Number Number Figure 1-1 S5PC110 Block Diagram ........................1-2 Figure 2-1 Address Map............................. 2-1 Figure 2-2 Internal Memory Address Map......................2-3...
Page 7: Overview Of S5Pc110
(MFC) supports real-time video conferencing and Analog TV out, HDMI for NTSC, and PAL mode. S5PC110 has an interface to external memory that is capable of sustaining heavy memory bandwidths required in high-end communication services. The memory system has Flash/ ROM external memory ports for parallel access and DRAM port to meet high bandwidths.
Page 8: Block Diagram Of S5Pc110
S5PC110_UM 1 OVERVIEW OF S5PC110 1.2 BLOCK DIAGRAM OF S5PC110 shows the complete block diagram of S5PC110. Figure 1-1 System Peripheral CPU Core Multimedia CortexA8 12 MP Camera IF / MIPI CSI-2 PLL x 4 32KB/32KB I/ D cache Timer with PWM (4ch) 800MHz/1 GHz @ 1.1V/1.2V...
Page 9: Key Features Of S5Pc110
S5PC110_UM 1 OVERVIEW OF S5PC110 1.3 KEY FEATURES OF S5PC110 The key features of S5PC110 include: • ARM CortexTM-A8 based CPU Subsystem with NEON − 32/ 32 KB I/D Cache, 512 KB L2 Cache − Operating frequency up to 800 MHz at 1.1V, 1 GHz at 1.2V •...
Page 10: Microprocessor
S5PC110_UM 1 OVERVIEW OF S5PC110 • 24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA) • Supports 14x8 key matrix • 10-channel 12-bit multiplexed ADC • Configurable GPIOs • Real time clock, PLL, timer with PWM and watch dog timer •...
Page 11: Memory Subsystem
S5PC110_UM 1 OVERVIEW OF S5PC110 1.3.2 MEMORY SUBSYSTEM The key features of memory subsystem include: • High bandwidth Memory Matrix subsystem • Two independent external memory ports (1 x16 Static Hybrid Memory port and 2 x32 DRAM port) • Matrix architecture increases the overall bandwidth with simultaneous access capability −...
Page 12: Multimedia
S5PC110_UM 1 OVERVIEW OF S5PC110 1.3.3 MULTIMEDIA The key features of multimedia include: • Camera Interface − Multiple input support ITU-R BT 601/656 mode DMA (AXI 64-bit interface) mode MIPI (CSI) mode − Multiple output support DMA (AXI 64-bit interface) mode Direct FIFO mode −...
Page 13 S5PC110_UM 1 OVERVIEW OF S5PC110 − ISO/IEC 13818-2 MPEG-2 Decoding supports Main Profile High level Decoding supports MPEG-1 except D-picture − SMPTE 421M VC-1 Decoding supports Simple Profile Medium Level/ Main Profile High Level/ Advanced Profile Level4 • JPEG Codec −...
Page 14 S5PC110_UM 1 OVERVIEW OF S5PC110 • Digital TV Interface − High-definition Multimedia Interface (HDMI) 1.3 − Supports up to 1080p 30Hz and 8-channel/ 112 kHz/ 24-bit audio − Supports 480p, 576p, 720p, 1080i, 1080p (cannot support 480i) − Supports HDCP v1.1 •...
Page 15: Audio Subsystem
S5PC110_UM 1 OVERVIEW OF S5PC110 1.3.4 AUDIO SUBSYSTEM The key features of audio subsystem include: • Audio processing is progressed by Reconfigurable Processor (RP) • Low power audio subsystem − 5.1ch I2S with 32-bit-width 64-depth FIFO − 128 KB audio play output buffer −...
Page 16: Connectivity
S5PC110_UM 1 OVERVIEW OF S5PC110 1.3.6 CONNECTIVITY The key features of connectivity include: • PCM Audio Interface − 16-bit mono audio interface − Master mode only − Supports three port PCM interface • AC97 Audio Interface − Independent channels for stereo PCM In, stereo PCM Out, and mono MIC In −...
Page 17 S5PC110_UM 1 OVERVIEW OF S5PC110 • UART − Four UART with DMA-based or interrupt-based operation − Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/ receive − Rx/Tx independent 256 byte FIFO for UART0, 64 byte FIFO for UART1 and 16 byte FIFO for UART2/3 −...
Page 18 S5PC110_UM 1 OVERVIEW OF S5PC110 • GPIO − 237 multi-functional input/ output ports − Controls 178 External Interrupts − GPA0: 8 in/out port – 2xUART with flow control − GPA1: 4 in/out port – 2xUART without flow control or 1xUART with flow control −...
Page 19: System Peripheral
S5PC110_UM 1 OVERVIEW OF S5PC110 1.3.7 SYSTEM PERIPHERAL The key features of system peripheral include: • Real Time Clock − Full clock features: sec, min, hour, date, day, month, and year − 32.768kHz operation − Alarm interrupt − Time-tick interrupt •...
Page 20 S5PC110_UM 1 OVERVIEW OF S5PC110 • Vectored Interrupt Controller − Software such as Interrupt device driver can mask out particular interrupt requests − Prioritization of interrupt sources for interrupt nesting • Power Management Clock-gating control for components − − Various low power modes are available such as Idle, Stop, Deep Stop, Deep Idle, and Sleep modes −...
Page 21: Conventions
S5PC110_UM 1 OVERVIEW OF S5PC110 1.4 CONVENTIONS 1.4.1 REGISTER R/W CONVENTIONS Symbol Definition Description Read Only The application has permission to read the Register field. Writes to read-only fields have no effect. Write Only The application has permission to write in the Register field.
Page 22: Memory Map
S5PC110_UM 2 MEMORY MAP MEMORY MAP This chapter describes the memory map available in S5PC110 processor. 2.1 MEMORY ADDRESS MAP 0 xFFFF _ FFFF SFRS 0 xE 000 _ 0000 0 xDFFF _ FFFF DMZ ROM 0 xD 000 _ 0000 IROM &...
Page 23: Device Specific Address Space
S5PC110_UM 2 MEMORY MAP 2.1.1 DEVICE SPECIFIC ADDRESS SPACE Address Size Description Note Mirrored region depending on 0x0000_0000 0x1FFF_FFFF 512MB Boot area the boot mode. 0x2000_0000 0x3FFF_FFFF 512MB DRAM 0 0x4000_0000 0x7FFF_FFFF 1024MB DRAM 1 0x8000_0000 0x87FF_FFFF 128MB SROM Bank 0 0x8800_0000 0x8FFF_FFFF 128MB...
Page 24 S5PC110_UM 2 MEMORY MAP 0xD000_0000 Secure iROM (64KB) area 0xD000_FFFF 0xD001_0000 Not Available 0xD001_FFFF 0xD002_0000 Secure area iRAM(128KB) Secure area 0xD003_FFFF 0xD004_0000 Not Available 0xD800_0000 DMZ ROM Secure area 0xDFFF_FFFF Figure 2-2 Internal Memory Address Map NOTE: TZPCR0SIZE[5:0](TZPC0); (in TZPC SFR) - 4KByte chunks - Recommended value: 6'b00_0000 ~ 6'b10_0000 * if (TZPCR0SIZE[5](TZPC0) == 1'b1), the full address range in iSRAM is configured as secure.
Page 25: Special Function Register Map
S5PC110_UM 2 MEMORY MAP 2.1.2 SPECIAL FUNCTION REGISTER MAP Address Description 0xE000_0000 0xE00F_FFFF CHIPID 0xE010_0000 0xE01F_FFFF SYSCON 0xE020_0000 0xE02F_FFFF GPIO 0xE030_0000 0xE03F_FFFF AXI_DMA 0xE040_0000 0xE04F_FFFF AXI_PSYS 0xE050_0000 0xE05F_FFFF AXI_PSFR 0xE060_0000 0xE06F_FFFF TZPC2 0xE070_0000 0xE07F_FFFF IEM_APC 0xE080_0000 0xE08F_FFFF IEM_IEC 0xE090_0000 0xE09F_FFFF PDMA0 0xE0A0_0000 0xE0AF_FFFF...
Page 26 S5PC110_UM 2 MEMORY MAP Address Description 0xE820_0000 0xE82F_FFFF CFCON 0xEA00_0000 0xEA0F_FFFF SECSS 0xEB00_0000 0xEB0F_FFFF SDMMC0 0xEB10_0000 0xEB1F_FFFF SDMMC1 0xEB20_0000 0xEB2F_FFFF SDMMC2 0xEB30_0000 0xEB3F_FFFF SDMMC3 0xEB40_0000 0xEB4F_FFFF 0xEC00_0000 0xEC0F_FFFF USBOTG 0xEC10_0000 0xEC1F_FFFF USBOTG_PHY_CON 0xEC20_0000 0xEC2F_FFFF USBHOST_EHCI 0xEC30_0000 0xEC3F_FFFF USBHOST_OHCI 0xED00_0000 0xED0F_FFFF MODEM 0xED10_0000 0xED1F_FFFF...
Page 27 S5PC110_UM 2 MEMORY MAP Address Description 0xF1F0_0000 0xF1FF_FFFF ASYNC_MSFR_MPERI 0xF200_0000 0xF20F_FFFF VIC0 0xF210_0000 0xF21F_FFFF VIC1 0xF220_0000 0xF22F_FFFF VIC2 0xF230_0000 0xF23F_FFFF VIC3 0xF280_0000 0xF28F_FFFF TZIC0 0xF290_0000 0xF29F_FFFF TZIC1 0xF2A0_0000 0xF2AF_FFFF TZIC2 0xF2B0_0000 0xF2BF_FFFF TZIC3 0xF300_0000 0xF3FF_FFFF 0xF800_0000 0xF80F_FFFF FIMD 0xF900_0000 0xF90F_FFFF TVENC 0xF910_0000 0xF91F_FFFF...
Page 28 Section 2 SYSTEM...
Page 29 General Purpose Input/ Output ..............2-2 2.1 Overview ..............................2-2 2.1.1 Features............................2-3 2.1.2 Input/ Output Configuration ......................2-3 2.1.3 S5PC110 Input/ Output Types......................2-3 2.1.4 IO Driver strength ..........................2-4 2.1.5 Input/ Output Description........................2-8 2.2 Register Description..........................2-25 2.2.1 Register Map ..........................2-25 2.2.2 Port Group GPA0 Control Register ....................
Page 30 2.2.35 Port Group MP1_3 Control Register................... 2-111 2.2.36 Port Group MP1_4 Control Register................... 2-112 2.2.37 Port Group MP1_5 Control Register................... 2-112 2.2.38 Port Group MP1_6 Control Register................... 2-113 2.2.39 Port Group MP1_7 Control Register................... 2-113 2.2.40 Port Group MP1_8 Control Register................... 2-114 2.2.41 Port Group MP2_0 Control Register...................
Page 31 3.7.9 Other SFRs............................. 3-57 3.7.10 IEM Control SFRs......................... 3-57 3.7.11 Miscellaneous SFRs........................3-63 Power Management..................4-1 4.1 Overview of PMU ............................. 4-1 4.2 FunctionAL Description of PMU....................... 4-2 4.3 System Power Mode..........................4-4 4.3.1 Overview............................4-4 4.3.2 Normal Mode ............................ 4-7 4.3.3 IDLE Mode............................
Page 32 5.2.2 IEM System Operation ........................5-9 5.3 IEM Implementation and Driver Setting ....................5-13 5.3.1 Definition of Performance ....................... 5-13 5.3.2 HPM Structure and Closed-Loop Behavior ..................5-14 5.3.3 Initialization Sequence........................5-17 5.4 I/O Description ............................5-18 5.5 Register Description..........................5-19 5.5.1 Register Map ..........................
Page 33 IEM Closed-Loop Voltage Generation Flow in HPM and APC1............. 5-14 Figure 5-5 IEM Closed-Loop Control Flow in APC1 HPM Delay ..............5-15 Figure 5-6 HPM Delay Tap structure in S5PC110 ................... 5-16 Figure 6-1 Block Diagram of Booting Time Operation ..................6-2 Figure 6-2 Total Booting Code Sequence Flow Chart ..................
Page 34 I/O Clocks in S5PC110 ........................3-13 Table 4-1 Comparison of Power Saving Techniques..................4-2 Table 4-2 S5PC110 Power Domains of Internal Logic ..................4-3 Table 4-3 Power Mode Summary ........................4-5 Table 4-4 Power Saving Mode Entering/Exiting Condition ................4-19 Table 4-5 Cortex-A8 Power Control .........................
Page 35: Chip Id
1.1 OVERVIEW OF CHIP ID The S5PC110 includes a Chip ID block for the software (SW) that sends and receives APB interface signals to the bus system. Chip ID is placed on the first address of the SFR region (0xE0000_0000).
Page 36: Register Description
1.2.1.1 Product ID Register (PRO_ID, R, Address = 0xE000_0000) PRO_ID Description Initial State Product ID [31:12] Product ID 0x43110 The product ID allocated to S5PC110 is “0x43110” Reserved [11:8] Reserved bits Rev. Number [7:4] Revision Number Device ID Device ID...
Page 37: General Purpose Input/ Output
GENERAL PURPOSE INPUT/ OUTPUT This chapter describes the General Purpose Input/ Output (GPIO). 2.1 OVERVIEW S5PC110 includes 237 multi-functional input/ output port pins and 142 memory port pins. There are 34 general port groups and 2 memory port groups as listed below: •...
Page 38: Features
Controls pin states in Sleep Mode except GPH0, GPH1, GPH2, and GPH3 ( GPH* pins are alive-pads) 2.1.2 INPUT/ OUTPUT CONFIGURATION Configurable Input/ Output (I/O) is subdivided into Type A and Type B. 2.1.3 S5PC110 INPUT/ OUTPUT TYPES I/O Types I/O Group...
Page 39: Io Driver Strength
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.1.4 IO DRIVER STRENGTH 2.1.4.1 Type A IO Driver Strength ( VDD=3.3V±0.3V) Currents Parameter Worst Typical Best VDD=3.00V VDD=3.30V VDD=3.60V T=125℃ T=25℃ T=-40℃ Process=Slow Process=Nominal Process=Fast Driver Type Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V...
Page 40 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT ( VDD=1.8V±0.15V) Currents Parameter Worst Typical Best VDD=1.65V VDD=1.80V VDD=1.95V T=12 ℃ T=25℃ T=-40℃ Process=Slow Process=Nominal Process=Fast Driver Type Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V Isink 2.263 mA...
Page 41 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT ( VDD=2.5V±0.2V ) Currents Parameter Worst Typical Best VDD=2.30V VDD=2.50V VDD=2.70V T=125℃ T=25℃ T=-40℃ Process=Slow Process=Nominal Process=Fast Driver Type Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at Isource at VDD*0.8V Isource at VDD*0.8V VDD*0.8V Isink 1.85mA...
Page 42 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.1.4.3 Type C IO Driver Strength ( VDD=1.8V±VDDx10% ) Currents Parameter Worst Typical Best VDD=1.65V VDD=1.80V VDD=1.95V T=125℃ T=25℃ T=-25℃ Process=Slow Process=Nominal Process=Fast Driver Type Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V...
Page 43: Input/ Output Description
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.1.5 INPUT/ OUTPUT DESCRIPTION 2.1.5.1 General Purpose Input/Output Block Diagram GPIO consists of two parts, namely, alive-part and off-part. In Alive-part power is supplied on sleep mode, but in off-part it is not the same. Therefore, the registers in alive-part keep their values during sleep mode. Register File Mux control Pad control...
Page 44 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.1.5.2 Pin Summary I/O Control Type Function Description Control at power down mode is possible, power down mode is released by S/W (ENABLE_GPIO bit of OTHERS register at PMU) Control at power down mode is possible, power down mode is released by S/W (ENABLE_UART_IO bit of OTHERS register at PMU) Control at power down mode is possible, power down mode is released by S/W (ENABLE_MMC_IO bit of OTHERS register at PMU)
Page 45 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.1.5.3 Pin Mux Description @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State XuRXD[0] GPA0[0] UART_0_RXD I(L) PBIDIRSE_G XuTXD[0] GPA0[1] UART_0_TXD I(L) PBIDIRSE_G XuCTSn[0] GPA0[2] UART_0_CTSn I(L) PBIDIRSE_G XuRTSn[0] GPA0[3] UART_0_RTSn I(L) PBIDIRSE_G...
Page 46 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State XpwmTOUT[3] GPD0[3] TOUT_3 I(L) PBIDIRSE_G Xi2c0SDA GPD1[0] I2C0_SDA I(L) PBIDIRSE_G Xi2c0SCL GPD1[1] I2C0_SCL I(L) PBIDIRSE_G Xi2c1SDA GPD1[2] I2C1_SDA I(L) PBIDIRSE_G Xi2c1SCL GPD1[3] I2C1_SCL I(L)
Page 47 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State XvVD[12] GPF2[0] LCD_VD[12] SYS_VD[12] V656_DATA[4] I(L) PBIDIRSE_G XvVD[13] GPF2[1] LCD_VD[13] SYS_VD[13] V656_DATA[5] I(L) PBIDIRSE_G XvVD[14] GPF2[2] LCD_VD[14] SYS_VD[14] V656_DATA[6] I(L) PBIDIRSE_G XvVD[15] GPF2[3] LCD_VD[15]...
Page 48 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State Xmmc3CMD GPG3[1] SD_3_CMD I(L) PBIDIRF_G Xmmc3CDn GPG3[2] SD_3_CDn I(L) PBIDIRF_G Xmmc3DATA[0] GPG3[3] SD_3_DATA[0] SD_2_DATA[4] I(L) PBIDIRF_G Xmmc3DATA[1] GPG3[4] SD_3_DATA[1] SD_2_DATA[5] I(L) PBIDIRF_G Xmmc3DATA[2] GPG3[5]...
Page 49 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State XEINT[30] GPH3[6] KP_ROW[6] I(L) PBIDIR_ALV XEINT[31] GPH3[7] KP_ROW[7] I(L) PBIDIR_ALV Xi2s0SCLK GPI[0] I2S_0_SCLK PCM_0_SCLK Func0 O(L) PBIDIRSE_G Xi2s0CDCLK GPI[1] I2S_0_CDCLK PCM_0_EXTCLK Func0 O(L) PBIDIRSE_G...
Page 50 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State XmsmDATA[6] GPJ2[6] MSM_DATA[6] KP_COL[7] CF_DATA[6] MHL_D13 I(L) PBIDIRSE_G XmsmDATA[7] GPJ2[7] MSM_DATA[7] KP_ROW[0] CF_DATA[7] MHL_D14 I(L) PBIDIRSE_G XmsmDATA[8] GPJ3[0] MSM_DATA[8] KP_ROW[1] CF_DATA[8] MHL_D15 I(L) PBIDIRSE_G...
Page 51 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State ONANDX Xm0FWEn MP0_3[2] NF_FWEn Func3 O(H) PBIDIRF_G L_RPn Xm0FREn MP0_3[3] NF_FREn Func3 PBIDIRF_G ONANDX Xm0FRnB[0] MP0_3[4] NF_RnB[0] Func3 PBIDIRF_G L_INT[0] ONANDX Xm0FRnB[1] MP0_3[5] NF_RnB[1]...
Page 52 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State Xm0DATA[12] MP0_7[4] EBI_DATA[12] Func0 O(L) PBIDIRF_G Xm0DATA[13] MP0_7[5] EBI_DATA[13] Func0 O(L) PBIDIRF_G Xm0DATA[14] MP0_7[6] EBI_DATA[14] Func0 O(L) PBIDIRF_G Xm0DATA[15] MP0_7[7] EBI_DATA[15] Func0 O(L) PBIDIRF_G...
Page 53 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State Xm1DATA[16] MP1_4[0] LD0_DATA[16] Func0 PBIDIR_MDDR Xm1DATA[17] MP1_4[1] LD0_DATA[17] Func0 PBIDIR_MDDR Xm1DATA[18] MP1_4[2] LD0_DATA[18] Func0 PBIDIR_MDDR Xm1DATA[19] MP1_4[3] LD0_DATA[19] Func0 PBIDIR_MDDR Xm1DATA[20] MP1_4[4] LD0_DATA[20] Func0...
Page 54 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State Xm1WEn MP1_8[4] LD0_WEn Func0 O(H) PBIDIR_MDDR Xm1GateIn MP1_8[5] LD0_IOGATE_IN Func0 PBIDIR_MDDR LD0_IOGATE_O Xm1GateOut MP1_8[6] Func0 PBIDIR_MDDR Xm2ADDR[0] MP2_0[0] LD1_ADDR[0] Func0 O(L) PBIDIR_MDDR Xm2ADDR[1] MP2_0[1]...
Page 55 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State Xm2DATA[16] MP2_4[0] LD1_DATA[16] Func0 PBIDIR_MDDR Xm2DATA[17] MP2_4[1] LD1_DATA[17] Func0 PBIDIR_MDDR Xm2DATA[18] MP2_4[2] LD1_DATA[18] Func0 PBIDIR_MDDR Xm2DATA[19] MP2_4[3] LD1_DATA[19] Func0 PBIDIR_MDDR Xm2DATA[20] MP2_4[4] LD1_DATA[20] Func0...
Page 56 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State Xm2WEn MP2_8[4] LD1_WEn Func0 O(H) PBIDIR_MDDR Xm2GateIn MP2_8[5] LD1_IOGATE_IN Func0 PBIDIR_MDDR LD1_IOGATE_O Xm2GateOut MP2_8[6] Func0 PBIDIR_MDDR XjTRSTn ETC0[0] XjTRSTn Func0 I(L) PBIDIRSE_G XjTMS ETC0[1]...
Page 57 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State XadcAIN[3] ANALOG AIN[3] Func0 PANALOGS XadcAIN[4] ANALOG AIN[4] Func0 PANALOGS XadcAIN[5] ANALOG AIN[5] Func0 PANALOGS XadcAIN[6] ANALOG AIN[6] Func0 PANALOGS XadcAIN[7] ANALOG AIN[7] Func0...
Page 58 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT @Reset Sleep Pin Name GPIO Func0 Func1 Func2 Func3 Default Pad Type State XmipiSDN2 ANALOG MIPI_SDN_2 Func0 PANALOGS XmipiSDN3 ANALOG MIPI_SDN_3 Func0 PANALOGS XmipiMDPCLK ANALOG MIPI_CLK_TX_P Func0 PANALOGS XmipiMDNCLK ANALOG MIPI_CLK_TX_N Func0 PANALOGS XmipiSDPCLK ANALOG MIPI_CLK_RX_P Func0...
Page 59 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.1.5.4 Pad Type Description Cell Name Function Description Wide-range I/O supply, programmable bi-direction I/O with cmos / schmitt PBIDIRSE_G trigger input, input disable, pull-up/down and 4-step strength output Wide-range I/O supply, programmable bi-direction Fast I/O with cmos / PBIDIRF_G schmitt trigger input, input disable, pull-up/down and 4-step strength output Wide-range I/O supply, programmable bi-direction I/O with cmos / schmitt...
Page 60: Register Description
Normal registers (For example, GPA0CON, GPA0DAT, GPA0PUD, and GPA0DRV) are the former, and power down registers (For example, GPA0CONPDN, and GPA0PUDPDN) are the latter. If, S5PC110 enter the power down mode, all configurations and Pull-down controls are selected by power down registers...
Page 61 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPC0PUD 0xE020_0068 Port Group GPC0 Pull-up/down Register 0x0155 GPC0DRV 0xE020_006C Port Group GPC0 Drive Strength Control 0x0000 Register GPC0CONPDN 0xE020_0070 Port Group GPC0 Power Down Mode 0x00 Configuration Register GPC0PUDPDN 0xE020_0074 Port Group GPC0 Power Down Mode Pull-...
Page 62 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPE0CONPDN 0xE020_00F0 Port Group GPE0 Power Down Mode 0x00 Configuration Register GPE0PUDPDN 0xE020_00F4 Port Group GPE0 Power Down Mode Pull- 0x00 up/down Register GPE1CON 0xE020_0100 Port Group GPE1 Configuration Register 0x00000000 GPE1DAT 0xE020_0104...
Page 63 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPF3CON 0xE020_0180 Port Group GPF3 Configuration Register 0x00000000 GPF3DAT 0xE020_0184 Port Group GPF3 Data Register 0x00 GPF3PUD 0xE020_0188 Port Group GPF3 Pull-up/down Register 0x0555 GPF3DRV 0xE020_018C Port Group GPF3 Drive Strength Control 0x0000 Register GPF3CONPDN...
Page 64 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPG3DRV 0xE020_020C Port Group GPG3 Drive Strength Control 0x0000 Register GPG3CONPDN 0xE020_0210 Port Group GPG3 Power Down Mode 0x00 Configuration Register GPG3PUDPDN 0xE020_0214 Port Group GPG3 Power Down Mode Pull- 0x00 up/ down Register GPICON...
Page 65 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPJ2PUDPDN 0xE020_0294 Port Group GPJ2 Power Down Mode Pull- 0x00 up/down Register GPJ3CON 0xE020_02A0 Port Group GPJ3 Configuration Register 0x00000000 GPJ3DAT 0xE020_02A4 Port Group GPJ3 Data Register 0x00 GPJ3PUD 0xE020_02A8 Port Group GPJ3 Pull-up/ down Register 0x5555...
Page 66 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value MP0_3PUD 0xE020_0328 Port Group MP0_3 Pull-up/down Register 0x0000 MP0_3DRV 0xE020_032C Port Group MP0_3 Drive Strength Control 0xAAAA Register MP0_3CONPDN 0xE020_0330 Port Group MP0_3 Power Down Mode 0x00 Configuration Register MP0_3PUDPDN 0xE020_0334 Port Group MP0_3 Power Down Mode Pull-...
Page 67 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value MP0_7CONPDN 0xE020_03B0 Port Group MP0_7 Power Down Mode 0x00 Configuration Register MP0_7PUDPDN 0xE020_03B4 Port Group MP0_7 Power Down Mode Pull- 0x00 up/down Register MP1_0CON 0xE020_03C0 Reserved (Do not use this register) 0x22222222 MP1_0DAT 0xE020_03C4...
Page 68 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value MP1_4PUDPDN 0xE020_0454 Reserved (Do not use this register) 0x00 MP1_5CON 0xE020_0460 Reserved (Do not use this register) 0x22222222 MP1_5DAT 0xE020_0464 Reserved (Do not use this register) 0x00 MP1_5PUD 0xE020_0468 Reserved (Do not use this register) 0x0000 MP1_5DRV...
Page 69 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value MP2_1PUD 0xE020_0508 Reserved (Do not use this register) 0x0000 MP2_1DRV 0xE020_050C Port Group MP2_1 Drive Strength Control 0xAAAA Register MP2_1CONPDN 0xE020_0510 Reserved (Do not use this register) 0x00 MP2_1PUDPDN 0xE020_0514 Reserved (Do not use this register) 0x00...
Page 70 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value MP2_6CONPDN 0xE020_05B0 Reserved (Do not use this register) 0x00 MP2_6PUDPDN 0xE020_05B4 Reserved (Do not use this register) 0x00 MP2_7CON 0xE020_05C0 Reserved (Do not use this register) 0x22222222 MP2_7DAT 0xE020_05C4 Reserved (Do not use this register) 0x00 MP2_7PUD...
Page 71 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPE0_INT_CON 0xE020_071C GPIO Interrupt GPE0_INT Configuration Register GPE1_INT_CON 0xE020_0720 GPIO Interrupt GPE1_INT Configuration Register GPF0_INT_CON 0xE020_0724 GPIO Interrupt GPF0_INT Configuration Register GPF1_INT_CON 0xE020_0728 GPIO Interrupt GPF1_INT Configuration Register GPF2_INT_CON 0xE020_072C GPIO Interrupt GPF2_INT Configuration Register...
Page 72 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPC0_INT_FLTCON0 0xE020_0818 GPIO Interrupt GPC0_INT Filter Configuration Register 0 GPC0_INT_FLTCON1 0xE020_081C GPIO Interrupt GPC0_INT Filter Configuration Register 1 GPC1_INT_FLTCON0 0xE020_0820 GPIO Interrupt GPC1_INT Filter Configuration Register 0 GPC1_INT_FLTCON1 0xE020_0824 GPIO Interrupt GPC1_INT Filter Configuration Register 1 GPD0_INT_FLTCON0...
Page 73 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPG0_INT_FLTCON1 0xE020_086C GPIO Interrupt GPG0_INT Filter Configuration Register 1 GPG1_INT_FLTCON0 0xE020_0870 GPIO Interrupt GPG1_INT Filter Configuration Register 0 GPG1_INT_FLTCON1 0xE020_0874 GPIO Interrupt GPG1_INT Filter Configuration Register 1 GPG2_INT_FLTCON0 0xE020_0878 GPIO Interrupt GPG2_INT Filter Configuration Register 0 GPG2_INT_FLTCON1...
Page 74 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPE0_INT_MASK 0xE020_091C GPIO Interrupt GPE0_INT Mask Register 0x000000FF GPE1_INT_MASK 0xE020_0920 GPIO Interrupt GPE1_INT Mask Register 0x0000001F GPF0_INT_MASK 0xE020_0924 GPIO Interrupt GPF0_INT Mask Register 0x000000FF GPF1_INT_MASK 0xE020_0928 GPIO Interrupt GPF1_INT Mask Register 0x000000FF GPF2_INT_MASK 0xE020_092C...
Page 75 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPG3_INT_PEND 0xE020_0A40 GPIO Interrupt GPG3_INT Pending Register GPJ0_INT_PEND 0xE020_0A44 GPIO Interrupt GPJ0_INT Pending Register GPJ1_INT_PEND 0xE020_0A48 GPIO Interrupt GPJ1_INT Pending Register GPJ2_INT_PEND 0xE020_0A4C GPIO Interrupt GPJ2_INT Pending Register GPJ3_INT_PEND 0xE020_0A50 GPIO Interrupt GPJ3_INT Pending Register GPJ4_INT_PEND...
Page 76 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPG0_INT_FIXPRI 0xE020_0B48 GPIO Interrupt 14 Fixed Priority Control 0x00 Register GPG1_INT_FIXPRI 0xE020_0B4C GPIO Interrupt 15 Fixed Priority Control 0x00 Register GPG2_INT_FIXPRI 0xE020_0B50 GPIO Interrupt 16 Fixed Priority Control 0x00 Register GPG3_INT_FIXPRI 0xE020_0B54...
Page 77 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value EXT_INT_1_CON 0xE020_0E04 External Interrupt EXT_INT[8] ~ EXT_INT[15] Configuration Register EXT_INT_2_CON 0xE020_0E08 External Interrupt EXT_INT[16] ~ EXT_INT[23] Configuration Register EXT_INT_3_CON 0xE020_0E0C External Interrupt EXT_INT[24] ~ EXT_INT[31] Configuration Register EXT_INT_0_FLTCON0 0xE020_0E80 External Interrupt EXT_INT[0] ~ EXT_INT[7] 0x80808080 Filter Configuration Register 0...
Page 78: Port Group Gpa0 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.2 PORT GROUP GPA0 CONTROL REGISTER There are six control registers, namely, GPA0CON, GPA0DAT, GPA0PUD, GPA0DRV, GPA0CONPDN and GPA0PUDPDN in the Port Group GPA0 Control Registers. 2.2.2.1 Port Group GPA0 Control Register (GPA0CON, R/W, Address = 0xE020_0000) GPA0CON Description Initial State...
Page 79 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.2.2 Port Group GPA0 Control Register (GPA0DAT, R/W, Address = 0xE020_0004) GPA0DAT Description Initial State GPA0DAT[7:0] [7:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 80: Port Group Gpa1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.3 PORT GROUP GPA1 CONTROL REGISTER There are six control registers, namely, GPA1CON, GPA1DAT, GPA1PUD, GPA1DRV, GPA1CONPDN and GPA1PUDPDN in the Port Group GPA1 Control Registers. 2.2.3.1 Port Group GPA1 Control Register (GPA1CON, R/W, Address = 0xE020_0020) GPA1CON Description Initial State...
Page 81 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.3.2 Port Group GPA1 Control Register (GPA1DAT, R/W, Address = 0xE020_0024) GPA1DAT Description Initial State GPA1DAT[3:0] [3:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 82: Port Group Gpb Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.4 PORT GROUP GPB CONTROL REGISTER There are six control registers, namely, GPBCON, GPBDAT, GPBPUD, GPBDRV, GPBCONPDN and GPBPUDPDN in the Port Group GPB Control Registers. 2.2.4.1 Port Group GPB Control Register (GPBCON, R/W, Address = 0xE020_0040) GPBCON Description Initial State...
Page 83 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.4.2 Port Group GPB Control Register (GPBDAT, R/W, Address = 0xE020_0044) GPBDAT Description Initial State GPBDAT[7:0] [7:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 84: Port Group Gpc0 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.5 PORT GROUP GPC0 CONTROL REGISTER There are six control registers, namely, GPC0CON, GPC0DAT, GPC0PUD, GPC0DRV, GPC0CONPDN and GPC0PUDPDN in the Port Group GPC0 Control Registers. 2.2.5.1 Port Group GPC0 Control Register (GPC0CON, R/W, Address = 0xE020_0060) GPC0CON Description Initial State...
Page 85 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.5.2 Port Group GPC0 Control Register (GPC0DAT, R/W, Address = 0xE020_0064) GPC0DAT Description Initial State GPC0DAT[4:0] [4:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 86: Port Group Gpc1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.6 PORT GROUP GPC1 CONTROL REGISTER There are six control registers, namely, GPC1CON, GPC1DAT, GPC1PUD, GPC1DRV, GPC1CONPDN and GPC1PUDPDN in the Port Group GPC1 Control Registers. 2.2.6.1 Port Group GPC1 Control Register (GPC1CON, R/W, Address = 0xE020_0080) GPC1CON Description Initial State...
Page 87 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.6.2 Port Group GPC1 Control Register (GPC1DAT, R/W, Address = 0xE020_0084) GPC1DAT Description Initial State GPC1DAT[4:0] [4:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 88: Port Group Gpd0 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.7 PORT GROUP GPD0 CONTROL REGISTER There are six control registers, namely, GPD0CON, GPD0DAT, GPD0PUD, GPD0DRV, GPD0CONPDN and GPD0PUDPDN in the Port Group GPD0 Control Registers. 2.2.7.1 Port Group GPD0 Control Register (GPD0CON, R/W, Address = 0xE020_00A0) GPD0CON Description Initial State...
Page 89 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.7.4 Port Group GPD0 Control Register (GPD0DRV, R/W, Address = 0xE020_00AC) GPD0DRV Description Initial State GPD0DRV[n] [2n+1:2n] 00 = 1x 0x0000 10 = 2x n=0~3 01 = 3x 11 = 4x 2.2.7.5 Port Group GPD0 Control Register (GPD0CONPDN, R/W, Address = 0xE020_00B0) GPD0CONPDN Description Initial State...
Page 90: Port Group Gpd1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.8 PORT GROUP GPD1 CONTROL REGISTER There are six control registers, namely, GPD1CON, GPD1DAT, GPD1PUD, GPD1DRV, GPD1CONPDN and GPD1PUDPDN in the Port Group GPD1 Control Registers. 2.2.8.1 Port Group GPD1 Control Register (GPD1CON, R/W, Address = 0xE020_00C0) GPD1CON Description Initial State...
Page 91 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.8.2 Port Group GPD1 Control Register (GPD1DAT, R/W, Address = 0xE020_00C4) GPD1DAT Description Initial State GPD1DAT[5:0] [5:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 92: Port Group Gpe0 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.9 PORT GROUP GPE0 CONTROL REGISTER There are six control registers, namely, GPE0CON, GPE0DAT, GPE0PUD, GPE0DRV, GPE0CONPDN and GPE0PUDPDN in the Port Group GPE0 Control Registers. 2.2.9.1 Port Group GPE0 Control Register (GPE0CON, R/W, Address = 0xE020_00E0) GPE0CON Description Initial State...
Page 93 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.9.2 Port Group GPE0 Control Register (GPE0DAT, R/W, Address = 0xE020_00E4) GPE0DAT Description Initial State GPE0DAT[7:0] [7:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 94: Port Group Gpe1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.10 PORT GROUP GPE1 CONTROL REGISTER There are six control registers, namely, GPE1CON, GPE1DAT, GPE1PUD, GPE1DRV, GPE1CONPDN and GPE1PUDPDN in the Port Group GPE1 Control Registers. 2.2.10.1 Port Group GPE1 Control Register (GPE1CON, R/W, Address = 0xE020_0100) GPE1CON Description Initial State...
Page 95 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.10.3 Port Group GPE1 Control Register (GPE1PUD, R/W, Address = 0xE020_0108) GPE1PUD Description Initial State GPE1PUD[n] [2n+1:2n] 00 = Pull-up/ down disabled 0x0155 01 = Pull-down enabled n=0~4 10 = Pull-up enabled 11 = Reserved 2.2.10.4 Port Group GPE1 Control Register (GPE1DRV, R/W, Address = 0xE020_010C) GPE1DRV Description...
Page 96: Port Group Gpf0 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.11 PORT GROUP GPF0 CONTROL REGISTER There are six control registers, namely, GPF0CON, GPF0DAT, GPF0PUD, GPF0DRV, GPF0CONPDN and GPF0PUDPDN in the Port Group GPF0 Control Registers. 2.2.11.1 Port Group GPF0 Control Register (GPF0CON, R/W, Address = 0xE020_0120) GPF0CON Description Initial State...
Page 97 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPF0CON Description Initial State GPF0CON[1] [7:4] 0000 = Input 0000 0001 = Output 0010 = LCD_VSYNC 0011 = SYS_CS1 0100 = VEN_VSYNC 0101 ~ 1110 = Reserved 1111 = GPF0_INT[1] GPF0CON[0] [3:0] 0000 = Input 0000 0001 = Output 0010 = LCD_HSYNC...
Page 98 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.11.5 Port Group GPF0 Control Register (GPF0CONPDN, R/W, Address = 0xE020_0130) GPF0CONPDN Description Initial State GPF0[n] [2n+1:2n] 00 = Output 0 0x00 01 = Output 1 n=0~7 10 = Input 11 = Previous state 2.2.11.6 Port Group GPF0 Control Register (GPF0PUDPDN, R/W, Address = 0xE020_0134) GPF0PUDPDN Description...
Page 99: Port Group Gpf1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.12 PORT GROUP GPF1 CONTROL REGISTER There are six control registers, namely, GPF1CON, GPF1DAT, GPF1PUD, GPF1DRV, GPF1CONPDN and GPF1PUDPDN in the Port Group GPF1 Control Registers. 2.2.12.1 Port Group GPF1 Control Register (GPF1CON, S/W, Address = 0xE020_0140) GPF1CON Description Initial State...
Page 100 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPF1CON Description Initial State GPF1CON[1] [7:4] 0000 = Input 0000 0001 = Output 0010 = LCD_VD[5] 0011 = SYS_VD[5] 0100 = VEN_DATA[5] 0101 ~ 1110 = Reserved 1111 = GPF1_INT[1] GPF1CON[0] [3:0] 0000 = Input 0000 0001 = Output 0010 = LCD_VD[4]...
Page 101 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.12.5 Port Group GPF1 Control Register (GPF1CONPDN, S/W, Address = 0xE020_0150) GPF1CONPDN Description Initial State GPF1[n] [2n+1:2n] 00 = Output 0 0x00 01 = Output 1 n=0~7 10 = Input 11 = Previous state 2.2.12.6 Port Group GPF1 Control Register (GPF1PUDPDN, S/W, Address = 0xE020_0154) GPF1PUDPDN Description...
Page 102: Port Group Gpf2 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.13 PORT GROUP GPF2 CONTROL REGISTER There are six control registers, namely, GPF2CON, GPF2DAT, GPF2PUD, GPF2DRV, GPF2CONPDN and GPF2PUDPDN in the Port Group GPF2 Control Registers. 2.2.13.1 Port Group GPF2 Control Register (GPF2CON, R/W, Address = 0xE020_0160) GPF2CON Description Initial State...
Page 103 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPF2CON Description Initial State GPF2CON[1] [7:4] 0000 = Input 0000 0001 = Output 0010 = LCD_VD[13] 0011 = SYS_VD[13] 0100 = V656_DATA[5] 0101 ~ 1110 = Reserved 1111 = GPF2_INT[1] GPF2CON[0] [3:0] 0000 = Input 0000 0001 = Output 0010 = LCD_VD[12]...
Page 104 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.13.5 Port Group GPF2 Control Register (GPF2CONPDN, S/W, Address = 0xE020_0170) GPF2CONPDN Description Initial State GPF2[n] [2n+1:2n] 00 = Output 0 0x00 01 = Output 1 n=0~7 10 = Input 11 = Previous state 2.2.13.6 Port Group GPF2 Control Register (GPF2PUDPDN, S/W, Address = 0xE020_0174) GPF2PUDPDN Description...
Page 105: Port Group Gpf3 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.14 PORT GROUP GPF3 CONTROL REGISTER There are six control registers, namely, GPF3CON, GPF3DAT, GPF3PUD, GPF3DRV, GPF3CONPDN and GPF3PUDPDN in the Port Group GPF3 Control Registers. 2.2.14.1 Port Group GPF3 Control Register (GPF3CON, R/W, Address = 0xE020_0180) GPF3CON Description Initial State...
Page 106 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.14.2 Port Group GPF3 Control Register (GPF3DAT, R/W, Address = 0xE020_0184) GPF3DAT Description Initial State GPF3DAT[5:0] [5:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 107: Port Group Gpg0 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.15 PORT GROUP GPG0 CONTROL REGISTER There are six control registers, namely, GPG0CON, GPG0DAT, GPG0PUD, GPG0DRV, GPG0CONPDN and GPG0PUDPDN in the Port Group GPG0 Control Registers. 2.2.15.1 Port Group GPG0 Control Register (GPG0CON, R/W, Address = 0xE020_01A0) GPG0CON Description Initial State...
Page 108 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.15.2 Port Group GPG0 Control Register (GPG0DAT, R/W, Address = 0xE020_01A4) GPG0DAT Description Initial State GPG0DAT[6:0] [6:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 109: Port Group Gpg1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.16 PORT GROUP GPG1 CONTROL REGISTER There are six control registers, namely, GPG1CON, GPG1DAT, GPG1PUD, GPG1DRV, GPG1CONPDN and GPG1PUDPDN in the Port Group GPG1 Control Registers. 2.2.16.1 Port Group GPG1 Control Register (GPG1CON, R/W, Address = 0xE020_01C0) GPG1CON Description Initial State...
Page 110 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.16.2 Port Group GPG1 Control Register (GPG1DAT, R/W, Address = 0xE020_01C4) GPG1DAT Description Initial State GPG1DAT[6:0] [6:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 111: Port Group Gpg2 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.17 PORT GROUP GPG2 CONTROL REGISTER There are six control registers, namely, GPG2CON, GPG2DAT, GPG2PUD, GPG2DRV, GPG2CONPDN and GPG2PUDPDN in the Port Group GPG2 Control Registers. 2.2.17.1 Port Group GPG2 Control Register (GPG2CON, R/W, Address = 0xE020_01E0) GPG2CON Description Initial State...
Page 112 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.17.2 Port Group GPG2 Control Register (GPG2DAT, R/W, Address = 0xE020_01E4) GPG2DAT Description Initial State [6:0] When the port is configured as input port, the corresponding GPG2DAT[6:0] 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 113: Port Group Gpg3 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.18 PORT GROUP GPG3 CONTROL REGISTER There are six control registers, namely, GPG3CON, GPG3DAT, GPG3PUD, GPG3DRV, GPG3CONPDN and GPG3PUDPDN in the Port Group GPG3 Control Registers. 2.2.18.1 Port Group GPG3 Control Register (GPG3CON, R/W, Address = 0xE020_0200) GPG3CON Description Initial State...
Page 114 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.18.2 Port Group GPG3 Control Register (GPG3DAT, R/W, Address = 0xE020_0204) GPG3DAT Description Initial State GPG3DAT[6:0] [6:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 115: Port Group Gpi Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.19 PORT GROUP GPI CONTROL REGISTER There are four control registers, namely, GPICON, GPIPUD and GPIDRV in the Port Group GPI Control Registers. This port group is used to only functional port (I2S_0 and PCM_0), not GPIO and EXT_INT. 2.2.19.1 Port Group GPI Control Register (GPICON, R/W, Address = 0xE020_0220) GPICON Description...
Page 116 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.19.4 Port Group GPI Control Register (GPIDRV, R/W, Address = 0xE020_022C) GPIDRV Description Initial State GPIDRV[n] [2n+1:2n] 00 = 1x 0x0000 10 = 2x n=0~6 01 = 3x 11 = 4x 2.2.19.5 Port Group GPI Control Register (GPICONPDN, R/W, Address = 0xE020_0230) GPICONPDN Description Initial State...
Page 117: Port Group Gpj0 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.20 PORT GROUP GPJ0 CONTROL REGISTER There are six control registers, namely, GPJ0CON, GPJ0DAT, GPJ0PUD, GPJ0DRV, GPJ0CONPDN and GPJ0PUDPDN in the Port Group GPJ0 Control Registers. 2.2.20.1 Port Group GPJ0 Control Register (GPJ0CON, R/W, Address = 0xE020_0240) GPJ0CON Description Initial State...
Page 118 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPJ0CON Description Initial State 0011 = CAM_B_DATA[2] 0100 = CF_ADDR[2] 0101 = TS_CLK 0110 ~ 1110 = Reserved 1111 = GPJ0_INT[2] GPJ0CON[1] [7:4] 0000 = Input 0000 0001 = Output 0010 = MSM_ADDR[1] 0011 = CAM_B_DATA[1] 0100 = CF_ADDR[1] 0101 = MIPI_ESC_CLK 0110 ~ 1110 = Reserved...
Page 119 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.20.4 Port Group GPJ0 Control Register (GPJ0DRV, R/W, Address = 0xE020_024C) GPJ0DRV Description Initial State GPJ0DRV[n] [2n+1:2n] 00 = 1x 0x0000 10 = 2x n=0~7 01 = 3x 11 = 4x 2.2.20.5 Port Group GPJ0 Control Register (GPJ0CONPDN, R/W, Address = 0xE020_0250) GPJ0CONPDN Description Initial State...
Page 120: Port Group Gpj1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.21 PORT GROUP GPJ1 CONTROL REGISTER There are six control registers, namely, GPJ1CON, GPJ1DAT, GPJ1PUD, GPJ1DRV, GPJ1CONPDN and GPJ1PUDPDN in the Port Group GPJ1 Control Registers. 2.2.21.1 Port Group GPJ1 Control Register (GPJ1CON, R/W, Address = 0xE020_0260) GPJ0CON Description Initial State...
Page 121 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.21.2 Port Group GPJ1 Control Register (GPJ1DAT, R/W, Address = 0xE020_0264) GPJ1DAT Description Initial State GPJ1DAT[5:0] [5:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 122: Port Group Gpj2 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.22 PORT GROUP GPJ2 CONTROL REGISTER There are six control registers, namely, GPJ2CON, GPJ2DAT, GPJ2PUD, GPJ2DRV, GPJ2CONPDN and GPJ2PUDPDN in the Port Group GPJ2 Control Registers. 2.2.22.1 Port Group GPJ2 Control Register (GPJ2CON, R/W, Address = 0xE020_0280) GPJ2CON Description Initial State...
Page 123 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPJ2CON Description Initial State 0011 = KP_COL[3] 0100 = CF_DATA[2] 0101 = MHL_D9 0110 ~ 1110 = Reserved 1111 = GPJ2_INT[2] GPJ2CON[1] [7:4] 0000 = Input 0000 0001 = Output 0010 = MSM_DATA[1] 0011 = KP_COL[2] 0100 = CF_DATA[1] 0101 = MHL_D8 0110 ~ 1110 = Reserved...
Page 124 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.22.4 Port Group GPJ2 Control Register (GPJ2DRV, R/W, Address = 0xE020_028C) GPJ2DRV Description Initial State GPJ2DRV[n] [2n+1:2n] 00 = 1x 0x0000 10 = 2x n=0~7 01 = 3x 11 = 4x 2.2.22.5 Port Group GPJ2 Control Register (GPJ2CONPDN, R/W, Address = 0xE020_0290) GPJ2CONPDN Description Initial State...
Page 125: Port Group Gpj3 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.23 PORT GROUP GPJ3 CONTROL REGISTER There are six control registers, namely, GPJ3CON, GPJ3DAT, GPJ3PUD, GPJ3DRV, GPJ3CONPDN and GPJ3PUDPDN in the Port Group GPJ3 Control Registers. 2.2.23.1 Port Group GPJ3 Control Register (GPJ3CON, R/W, Address = 0xE020_02A0) GPJ3CON Description Initial State...
Page 126 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPJ3CON Description Initial State 0011 = KP_ROW[3] 0100 = CF_DATA[10] 0101 = MHL_D17 0110 ~ 1110 = Reserved 1111 = GPJ3_INT[2] GPJ3CON[1] [7:4] 0000 = Input 0000 0001 = Output 0010 = MSM_DATA[9] 0011 = KP_ROW[2] 0100 = CF_DATA[9] 0101 = MHL_D16 0110 ~ 1110 = Reserved...
Page 127 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.23.4 Port Group GPJ3 Control Register (GPJ3DRV, R/W, Address = 0xE020_02AC) GPJ3DRV Description Initial State GPJ3DRV[n] [2n+1:2n] 00 = 1x 0x0000 10 = 2x n=0~7 01 = 3x 11 = 4x 2.2.23.5 Port Group GPJ3 Control Register (GPJ3CONPDN, R/W, Address = 0xE020_02B0) GPJ3CONPDN Description Initial State...
Page 128: Port Group Gpj4 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.24 PORT GROUP GPJ4 CONTROL REGISTER There are six control registers, namely, GPJ4CON, GPJ4DAT, GPJ4PUD, GPJ4DRV, GPJ4CONPDN and GPJ4PUDPDN in the Port Group GPJ4 Control Registers. 2.2.24.1 Port Group GPJ4 Control Register (GPJ4CON, R/W, Address = 0xE020_02C0) GPJ4CON Description Initial State...
Page 129 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.24.2 Port Group GPJ4 Control Register (GPJ4DAT, R/W, Address = 0xE020_02C4) GPJ4DAT Description Initial State GPJ4DAT[4:0] [4:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 130: Port Group Mp0_1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.25 PORT GROUP MP0_1 CONTROL REGISTER There are six control registers, namely, MP0_1CON, MP0_1DAT, MP0_1PUD, MP0_1DRV, MP0_1CONPDN and MP0_1PUDPDN in the Port Group MP0_1 Control Registers. 2.2.25.1 Port Group MP0_1 Control Register (MP0_1CON, R/W, Address = 0xE020_02E0) MP0_1CON Description Initial State...
Page 131 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.25.2 Port Group MP0_1 Control Register (MP0_1DAT, R/W, Address = 0xE020_02E4) MP0_1DAT Description Initial State MP0_1DAT[7:0] [7:0] When the port is configured as input port, the 0x00 corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 132: Port Group Mp0_2 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.26 PORT GROUP MP0_2 CONTROL REGISTER There are six control registers, namely, MP0_2CON, MP0_2DAT, MP0_2PUD, MP0_2DRV, MP0_2CONPDN and MP0_2PUDPDN in the Port Group MP0_2 Control Registers. 2.2.26.1 Port Group MP0_2 Control Register (MP0_2CON, R/W, Address = 0xE020_0300) MP0_2CON Description Initial State...
Page 133 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.26.3 Port Group MP0_2 Control Register (MP0_2PUD, R/W, Address = 0xE020_0308) MP0_2PUD Description Initial State MP0_2PUD[n] [2n+1:2n] 00 = Pull-up/ down disabled 0x0000 01 = Pull-down enabled n=0~3 10 = Pull-up enabled 11 = Reserved 2.2.26.4 Port Group MP0_2 Control Register (MP0_2DRV, R/W, Address = 0xE020_030C) MP0_2DRV Description...
Page 134: Port Group Mp0_3 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.27 PORT GROUP MP0_3 CONTROL REGISTER There are six control registers, namely, MP0_3CON, MP0_3DAT, MP0_3PUD, MP0_3DRV, MP0_3CONPDN and MP0_3PUDPDN in the Port Group MP0_3 Control Registers. 2.2.27.1 Port Group MP0_3 Control Register (MP0_3CON, R/W, Address = 0xE020_0320) MP0_3CON Description Initial State...
Page 135 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT MP0_3CON Description Initial State 0011 = Reserved 0100 = Reserved 0101 = ONANDXL_SMCLK 0110 ~ 1110 = Reserved 1111 = Reserved MP0_3CON[0] [3:0] 0000 = Input 0101 0001 = Output 0010 = NF_CLE 0011 = Reserved 0100 = Reserved 0101 = ONANDXL_ADDRVALID 0110 ~ 1110 = Reserved...
Page 136 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.27.5 Port Group MP0_3 Control Register (MP0_3CONPDN, R/W, Address = 0xE020_0330) MP0_3CONPDN Description Initial State MP0_3[n] [2n+1:2n] 00 = Output 0 0x00 01 = Output 1 n=0~7 10 = Input 11 = Previous state 2.2.27.6 Port Group MP0_3 Control Register (MP0_3PUDPDN, R/W, Address = 0xE020_0334) MP0_3PUDPDN Description...
Page 137: Port Group Mp0_4 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.28 PORT GROUP MP0_4 CONTROL REGISTER There are six control registers, namely, MP0_4CON, MP0_4DAT, MP0_4PUD, MP0_4DRV, MP0_4CONPDN and MP0_4PUDPDN in the Port Group MP0_4 Control Registers. 2.2.28.1 Port Group MP0_4 Control Register (MP0_4CON, R/W, Address = 0xE020_0340) MP0_4CON Description Initial State...
Page 138 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.28.2 Port Group MP0_4 Control Register (MP0_4DAT, R/W, Address = 0xE020_0344) MP0_4DAT Description Initial State MP0_4DAT[7:0] [7:0] When the port is configured as input port, the 0x00 corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 139: Port Group Mp0_5 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.29 PORT GROUP MP0_5 CONTROL REGISTER There are six control registers, namely, MP0_5CON, MP0_5DAT, MP0_5PUD, MP0_5DRV, MP0_5CONPDN and MP0_5PUDPDN in the Port Group MP0_5 Control Registers. 2.2.29.1 Port Group MP0_5 Control Register (MP0_5CON, R/W, Address = 0xE020_0360) MP0_5CON Description Initial State...
Page 140 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.29.2 Port Group MP0_5 Control Register (MP0_5DAT, R/W, Address = 0xE020_0364) MP0_5DAT Description Initial State MP0_5DAT[7:0] [7:0] When the port is configured as input port, the 0x00 corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 141: Port Group Mp0_6 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.30 PORT GROUP MP0_6 CONTROL REGISTER There are six control registers, namely, MP0_6CON, MP0_6DAT, MP0_6PUD, MP0_6DRV, MP0_6CONPDN and MP0_6PUDPDN in the Port Group MP0_6 Control Registers. 2.2.30.1 Port Group MP0_6 Control Register (MP0_6CON, R/W, Address = 0xE020_0380) MP0_6CON Description Initial State...
Page 142 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.30.2 Port Group MP0_6 Control Register (MP0_6DAT, R/W, Address = 0xE020_0384) MP0_6DAT Description Initial State MP0_6DAT[7:0] [7:0] When the port is configured as input port, the 0x00 corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 143: Port Group Mp0_7 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.31 PORT GROUP MP0_7 CONTROL REGISTER There are six control registers, namely, MP0_7CON, MP0_7DAT, MP0_7PUD, MP0_7DRV, MP0_7CONPDN and MP0_7PUDPDN in the Port Group MP0_7 Control Registers. 2.2.31.1 Port Group MP0_7 Control Register (MP0_7CON, R/W, Address = 0xE020_03A0) MP0_7CON Description Initial State...
Page 144 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.31.2 Port Group MP0_7 Control Register (MP0_7DAT, R/W, Address = 0xE020_03A4) MP0_7DAT Description Initial State MP0_7DAT[7:0] [7:0] When the port is configured as input port, the 0x00 corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 145: Port Group Mp1_0 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.32 PORT GROUP MP1_0 CONTROL REGISTER There are six control registers, namely, MP1_0CON, MP1_0DAT, MP1_0PUD, MP1_0DRV, MP1_0CONPDN and MP1_0PUDPDN in the Port Group MP1_0 Control Registers. • MP1_0CON, R/W, Address = 0xE020_03C0 • MP1_0DAT, R/W, Address = 0xE020_03C4 •...
Page 146: Port Group Mp1_2 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.34 PORT GROUP MP1_2 CONTROL REGISTER There are six control registers, namely, MP1_2CON, MP1_2DAT, MP1_2PUD, MP1_2DRV, MP1_2CONPDN and MP1_2PUDPDN in the Port Group MP1_2 Control Registers. • MP1_2CON, R/W, Address = 0xE020_0400 • MP1_2DAT, R/W, Address = 0xE020_0404 •...
Page 147: Port Group Mp1_4 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.36 PORT GROUP MP1_4 CONTROL REGISTER There are six control registers, namely, MP1_4CON, MP1_4DAT, MP1_4PUD, MP1_4DRV, MP1_4CONPDN and MP1_4PUDPDN in the Port Group MP1_4 Control Registers. • MP1_4CON, R/W, Address = 0xE020_0440 • MP1_4DAT, R/W, Address = 0xE020_0444 •...
Page 148: Port Group Mp1_6 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.38 PORT GROUP MP1_6 CONTROL REGISTER There are six control registers, namely, MP1_6CON, MP1_6DAT, MP1_6PUD, MP1_6DRV, MP1_6CONPDN and MP1_6PUDPDN in the Port Group MP1_6 Control Registers. • MP1_6CON, R/W, Address = 0xE020_0480 • MP1_6DAT, R/W, Address = 0xE020_0484 •...
Page 149: Port Group Mp1_8 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.40 PORT GROUP MP1_8 CONTROL REGISTER There are six control registers, namely, MP1_8CON, MP1_8DAT, MP1_8PUD, MP1_8DRV, MP1_8CONPDN and MP1_8PUDPDN in the Port Group MP1_8 Control Registers. • MP1_8CON, R/W, Address = 0xE020_04C0 • MP1_8DAT, R/W, Address = 0xE020_04C4 •...
Page 150: Port Group Mp2_1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.42 PORT GROUP MP2_1 CONTROL REGISTER There are six control registers, namely, MP2_1CON, MP2_1DAT, MP2_1PUD, MP2_1DRV, MP2_1CONPDN and MP2_1PUDPDN in the Port Group MP2_1 Control Registers. • MP2_1CON, R/W, Address = 0xE020_0500 • MP2_1DAT, R/W, Address = 0xE020_0504 •...
Page 151: Port Group Mp2_3 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.44 PORT GROUP MP2_3 CONTROL REGISTER There are six control registers, namely, MP2_3CON, MP2_3DAT, MP2_3PUD, MP2_3DRV, MP2_3CONPDN and MP2_3PUDPDN in the Port Group MP2_3 Control Registers. • MP2_3CON, R/W, Address = 0xE020_0540 • MP2_3DAT, R/W, Address = 0xE020_0544 •...
Page 152: Port Group Mp2_5 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.46 PORT GROUP MP2_5 CONTROL REGISTER There are six control registers, namely, MP2_5CON, MP2_5DAT, MP2_5PUD, MP2_5DRV, MP2_5CONPDN and MP2_5PUDPDN in the Port Group MP2_5 Control Registers. • MP2_5CON, R/W, Address = 0xE020_0580 • MP2_5DAT, R/W, Address = 0xE020_0584 •...
Page 153: Port Group Mp2_7 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.48 PORT GROUP MP2_7 CONTROL REGISTER There are six control registers, namely, MP2_7CON, MP2_7DAT, MP2_7PUD, MP2_7DRV, MP2_7CONPDN and MP2_7PUDPDN in the Port Group MP2_7 Control Registers. • MP2_7CON, R/W, Address = 0xE020_05C0 • MP2_7DAT, R/W, Address = 0xE020_05C4 •...
Page 154: Port Group Etc0 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.50 PORT GROUP ETC0 CONTROL REGISTER There are two control registers, namely, ETC0PUD and ETC0DRV. ETC0 ports are dedicated as shown in table below: ETC0 Pin Name Description Initial State ETC0[0] XjTRSTn JTAG TAP Controller Reset ETC0[1] XjTMS JTAG TAP Controller Mode Select...
Page 155: Port Group Etc1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.51 PORT GROUP ETC1 CONTROL REGISTER There are two control registers, namely, ETC1PUD and ETC1DRV. ETC1 ports are dedicated as shown in table below: ETC1 Pin Name Description Initial State ETC1[0] XOM[0] Operating Mode control signal 0 ETC1[1] XOM[1] Operating Mode control signal 1...
Page 156 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.51.2 Port Group ETC1 Control Register (ETC1DRV, R/W, Address = 0xE020_062C) ETC1DRV Description Initial State ETC1DRV[n] [2n+1:2n] Reserved(fixed) n=0~5 ETC1DRV[0] : 01 (3x) ETC1DRV[1] : 01 (3x) ETC1DRV[2] : 01 (3x) ETC1DRV[3] : 01 (3x) ETC1DRV[4] : 01 (3x) ETC1DRV[5] : 01 (3x) ETC1DRV[6]...
Page 157: Port Group Etc2 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.52 PORT GROUP ETC2 CONTROL REGISTER There are two control registers, namely, ETC2PUD and ETC2DRV. ETC2 ports are dedicated as shown in table below: ETC2 Pin Name Description Initial State ETC2[0] XnRESET System Reset ETC2[1] CLKOUT Clock out signal...
Page 158 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.52.2 Port Group ETC2 Control Register (ETC2DRV, R/W, Address = 0xE020_064C) ETC2DRV Description Initial State ETC2DRV[0] [1:0] Reserved(fixed) ETC2DRV[0] : 01 (3x) ETC2DRV[1] [3:2] 00 = 1x 10 = 2x 01 = 3x 11 = 4x ETC2DRV[n] [2n+1:2n] Reserved(fixed)
Page 159: Port Group Etc3 Is Reserved
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.53 PORT GROUP ETC3 IS RESERVED 2.2.54 PORT GROUP ETC4 There is no registers. ETC4 ports are dedicated as shown in table below: ETC4 Pin Name Description Initial State ETC4[0] XrtcXTI 32 KHz crystal input for RTC ETC4[1] XrtcXTO 32 KHz crystal output for RTC...
Page 160 GPF0, GPF1, GPF2, GPF3, GPG0, GPG1, GPG2, GPG3, GPJ0, GPJ1, GPJ2, GPJ3 and GPJ4. In interrupt function, it is important to understand the filter operation. S5PC110 uses two types of filters to detect interrupt, namely, delay filter and digital filter. Delay filter uses delay cell.
Page 161 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value Register GPE1_INT_CON 0xE020_0720 GPIO Interrupt GPE1_INT Configuration Register GPF0_INT_CON 0xE020_0724 GPIO Interrupt GPF0_INT Configuration Register GPF1_INT_CON 0xE020_0728 GPIO Interrupt GPF1_INT Configuration Register GPF2_INT_CON 0xE020_072C GPIO Interrupt GPF2_INT Configuration Register GPF3_INT_CON 0xE020_0730 GPIO Interrupt GPF3_INT Configuration...
Page 162 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value Configuration Register 0 GPC0_INT_FLTCON1 0xE020_081C GPIO Interrupt GPC0_INT Filter Configuration Register 1 GPC1_INT_FLTCON0 0xE020_0820 GPIO Interrupt GPC1_INT Filter Configuration Register 0 GPC1_INT_FLTCON1 0xE020_0824 GPIO Interrupt GPC1_INT Filter Configuration Register 1 GPD0_INT_FLTCON0 0xE020_0828 GPIO Interrupt GPD0_INT Filter...
Page 163 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value Configuration Register 1 GPG1_INT_FLTCON0 0xE020_0870 GPIO Interrupt GPG1_INT Filter Configuration Register 0 GPG1_INT_FLTCON1 0xE020_0874 GPIO Interrupt GPG1_INT Filter Configuration Register 1 GPG2_INT_FLTCON0 0xE020_0878 GPIO Interrupt GPG2_INT Filter Configuration Register 0 GPG2_INT_FLTCON1 0xE020_087C GPIO Interrupt GPG2_INT Filter...
Page 164 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPE1_INT_MASK 0xE020_0920 GPIO Interrupt GPE1_INT Mask Register 0x0000001F GPF0_INT_MASK 0xE020_0924 GPIO Interrupt GPF0_INT Mask Register 0x000000FF GPF1_INT_MASK 0xE020_0928 GPIO Interrupt GPF1_INT Mask Register 0x000000FF GPF2_INT_MASK 0xE020_092C GPIO Interrupt GPF2_INT Mask Register 0x000000FF GPF3_INT_MASK 0xE020_0930...
Page 165 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPG0_INT_PEND 0xE020_0A34 GPIO Interrupt GPG0_INT Pending Register GPG1_INT_PEND 0xE020_0A38 GPIO Interrupt GPG1_INT Pending Register GPG2_INT_PEND 0xE020_0A3C GPIO Interrupt GPG2_INT Pending Register GPG3_INT_PEND 0xE020_0A40 GPIO Interrupt GPG3_INT Pending Register GPJ0_INT_PEND 0xE020_0A44 GPIO Interrupt GPJ0_INT Pending Register...
Page 166 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT Register Address Description Reset Value GPE1_INT_FIXPRI 0xE020_0B34 GPIO Interrupt 9 Fixed Priority Control 0x00 Register GPF0_INT_FIXPRI 0xE020_0B38 GPIO Interrupt 10 Fixed Priority Control 0x00 Register GPF1_INT_FIXPRI 0xE020_0B3C GPIO Interrupt 11 Fixed Priority Control 0x00 Register GPF2_INT_FIXPRI 0xE020_0B40...
Page 167 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.1 GPIO Interrupt Control Registers (GPA0_INT_CON, R/W, Address = 0xE020_0700) GPA0_INT_CON Description Initial State Reserved [31] Reserved GPA0_INT_CON[7] [30:28] Sets the signaling method of GPA0_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 168 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPA0_INT_CON Description Initial State 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPA0_INT_CON[1] [6:4] Sets the signaling method of GPA0_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 169 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.2 GPIO Interrupt Control Registers (GPA1_INT_CON, R/W, Address = 0xE020_0704) GPA1_INT_CON Description Initial State Reserved [31:16] Reserved Reserved [15] Reserved GPA1_INT_CON[3] [14:12] Sets the signaling method of GPA1_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 170 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.3 GPIO Interrupt Control Registers (GPB_INT_CON, R/W, Address = 0xE020_0708) GPB_INT_CON Description Initial State Reserved [31] Reserved GPB_INT_CON[7] [30:28] Sets the signaling method of GPB_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 171 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPB_INT_CON Description Initial State 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPB_INT_CON[1] [6:4] Sets the signaling method of GPB_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 172 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.4 GPIO Interrupt Control Registers (GPC0_INT_CON, R/W, Address = 0xE020_070C) GPC0_INT_CON Description Initial State Reserved [31:20] Reserved Reserved [19] Reserved GPC0_INT_CON[4] [18:16] Sets the signaling method of GPC0_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 173 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.5 GPIO Interrupt Control Registers (GPC1_INT_CON, R/W, Address = 0xE020_0710) GPC1_INT_CON Description Initial State Reserved [31:20] Reserved Reserved [19] Reserved GPC1_INT_CON[4] [18:16] Sets the signaling method of GPC1_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 174 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.6 GPIO Interrupt Control Registers (GPD0_INT_CON, R/W, Address = 0xE020_0714) GPD0_INT_CON Description Initial State Reserved [31:16] Reserved Reserved [15] Reserved GPD0_INT_CON[3] [14:12] Sets the signaling method of GPD0_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 175 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.7 GPIO Interrupt Control Registers (GPD1_INT_CON, R/W, Address = 0xE020_0718) GPD1_INT_CON Description Initial State Reserved [31:24] Reserved Reserved [23] Reserved GPD1_INT_CON[5] [22:20] Sets the signaling method of GPD1_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 176 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.8 GPIO Interrupt Control Registers (GPE0_INT_CON, R/W, Address = 0xE020_071C) GPE0_INT_CON Description Initial State Reserved [31] Reserved GPE0_INT_CON[7] [30:28] Sets the signaling method of GPE0_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 177 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPE0_INT_CON Description Initial State 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPE0_INT_CON[1] [6:4] Sets the signaling method of GPE0_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered...
Page 178 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.9 GPIO Interrupt Control Registers (GPE1_INT_CON, R/W, Address = 0xE020_0720) GPE1_INT_CON Description Initial State Reserved [31:20] Reserved Reserved [19] Reserved GPE1_INT_CON[4] [18:16] Sets the signaling method of GPE1_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 179 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.10 GPIO Interrupt Control Registers (GPF0_INT_CON, R/W, Address = 0xE020_0724) GPF0_INT_CON Description Initial State Reserved [31] Reserved GPF0_INT_CON[7] [30:28] Sets the signaling method of GPF0_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 180 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPF0_INT_CON Description Initial State 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPF0_INT_CON[1] [6:4] Sets the signaling method of GPF0_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 181 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.11 GPIO Interrupt Control Registers (GPF1_INT_CON, R/W, Address = 0xE020_0728) GPF1_INT_CON Description Initial State Reserved [31] Reserved GPF1_INT_CON[7] [30:28] Sets the signaling method of GPF1_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 182 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPF1_INT_CON Description Initial State 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPF1_INT_CON[1] [6:4] Sets the signaling method of GPF1_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 183 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.12 GPIO Interrupt Control Registers (GPF2_INT_CON, R/W, Address = 0xE020_072C) GPF2_INT_CON Description Initial State Reserved [31] Reserved GPF2_INT_CON[7] [30:28] Sets the signaling method of GPF2_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 184 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPF2_INT_CON Description Initial State 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPF2_INT_CON[1] [6:4] Sets the signaling method of GPF2_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 185 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.13 GPIO Interrupt Control Registers (GPF3_INT_CON, R/W, Address = 0xE020_0730) GPF3_INT_CON Description Initial State Reserved [31:24] Reserved Reserved [23] Reserved GPF3_INT_CON[5] [22:20] Sets the signaling method of GPF3_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 186 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.14 GPIO Interrupt Control Registers (GPG0_INT_CON, R/W, Address = 0xE020_0734) GPG0_INT_CON Description Initial State Reserved [31:28] Reserved Reserved [27] Reserved GPG0_INT_CON[6] [26:24] Sets the signaling method of GPG0_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 187 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPG0_INT_CON Description Initial State 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPG0_INT_CON[0] [2:0] Sets the signaling method of GPG0_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered...
Page 188 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.15 GPIO Interrupt Control Registers (GPG1_INT_CON, R/W, Address = 0xE020_0738) GPG1_INT_CON Description Initial State Reserved [31:28] Reserved Reserved [27] Reserved GPG1_INT_CON[6] [26:24] Sets the signaling method of GPG1_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 189 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPG1_INT_CON Description Initial State 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPG1_INT_CON[0] [2:0] Sets the signaling method of GPG1_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered...
Page 190 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.16 GPIO Interrupt Control Registers (GPG2_INT_CON, R/W, Address = 0xE020_073C) GPG2_INT_CON Description Initial State Reserved [31:28] Reserved Reserved [27] Reserved GPG2_INT_CON[6] [26:24] Sets the signaling method of GPG2_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 191 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPG2_INT_CON Description Initial State 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPG2_INT_CON[0] [2:0] Sets the signaling method of GPG2_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered...
Page 192 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.17 GPIO Interrupt Control Registers (GPG3_INT_CON, R/W, Address = 0xE020_0740) GPG3_INT_CON Description Initial State Reserved [31:28] Reserved Reserved [27] Reserved GPG3_INT_CON[6] [26:24] Sets the signaling method of GPG3_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 193 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPG3_INT_CON Description Initial State 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPG3_INT_CON[0] [2:0] Sets the signaling method of GPG3_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered...
Page 194 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.18 GPIO Interrupt Control Registers (GPJ0_INT_CON, R/W, Address = 0xE020_0744) GPJ0_INT_CON Description Initial State Reserved [31] Reserved GPJ0_INT_CON[7] [30:28] Sets the signaling method of GPJ0_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 195 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPJ0_INT_CON Description Initial State 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPJ0_INT_CON[1] [6:4] Sets the signaling method of GPJ0_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 196 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.19 GPIO Interrupt Control Registers (GPJ1_INT_CON, R/W, Address = 0xE020_0748) GPJ1_INT_CON Description Initial State Reserved [31:24] Reserved Reserved [23] Reserved GPJ1_INT_CON[5] [22:20] Sets the signaling method of GPJ1_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 197 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.20 GPIO Interrupt Control Registers (GPJ2_INT_CON, R/W, Address = 0xE020_074C) GPJ2_INT_CON Description Initial State Reserved [31] Reserved GPJ2_INT_CON[7] [30:28] Sets the signaling method of GPJ2_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 198 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPJ2_INT_CON Description Initial State 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPJ2_INT_CON[1] [6:4] Sets the signaling method of GPJ2_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 199 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.21 GPIO Interrupt Control Registers (GPJ3_INT_CON, R/W, Address = 0xE020_0750) GPJ3_INT_CON Description Initial State Reserved [31] Reserved GPJ3_INT_CON[7] [30:28] Sets the signaling method of GPJ3_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 200 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPJ3_INT_CON Description Initial State 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved GPJ3_INT_CON[1] [6:4] Sets the signaling method of GPJ3_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 201 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.22 GPIO Interrupt Control Registers (GPJ4_INT_CON, R/W, Address = 0xE020_0754) GPJ4_INT_CON Description Initial State Reserved [31:20] Reserved Reserved [19] Reserved GPJ4_INT_CON[4] [18:16] Sets the signaling method of GPJ4_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered...
Page 202 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.23 GPIO Interrupt Control Registers (GPA0_INT_FLTCON0, R/W, Address = 0xE020_0800) GPA0_INT_FLTCON0 Description Initial State FLTEN1[3] [31] Filter Enable for GPA0_INT[3] 0 = Disables 1 = Enables FLTWIDTH1[3] [30:24] Filtering width of GPA0_INT[3] This value is valid when FLTSEL1is 1. FLTEN1[2] [23] Filter Enable for GPA0_INT[2]...
Page 203 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.24 GPIO Interrupt Control Registers (GPA0_INT_FLTCON1, R/W, Address = 0xE020_0804) GPA0_INT_FLTCON1 Description Initial State FLTEN1[7] [31] Filter Enable for GPA0_INT[7] 0 = Disables 1 = Enables FLTWIDTH1[7] [30:24] Filtering width of GPA0_INT[7] This value is valid when FLTSEL1is 1. FLTEN1[6] [23] Filter Enable for GPA0_INT[6]...
Page 204 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.25 GPIO Interrupt Control Registers (GPA1_INT_FLTCON0, R/W, Address = 0xE020_0808) GPA1_INT_FLTCON0 Description Initial State FLTEN2[3] [31] Filter Enable for GPA1_INT[3] 0 = Disables 1 = Enables FLTWIDTH2[3] [30:24] Filtering width of GPA1_INT[3] This value is valid when FLTSEL2is 1. FLTEN2[2] [23] Filter Enable for GPA1_INT[2]...
Page 205 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.27 GPIO Interrupt Control Registers (GPB_INT_FLTCON0, R/W, Address = 0xE020_0810) GPB_INT_FLTCON0 Description Initial State FLTEN3[3] [31] Filter Enable for GPB_INT[3] 0 = Disables 1 = Enables FLTWIDTH3[3] [30:24] Filtering width of GPB_INT[3] This value is valid when FLTSEL3 is 1. FLTEN3[2] [23] Filter Enable for GPB_INT[2]...
Page 206 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.28 GPIO Interrupt Control Registers (GPB_INT_FLTCON1, R/W, Address = 0xE020_0814) GPB_INT_FLTCON1 Description Initial State FLTEN3[7] [31] Filter Enable for GPB_INT[7] 0 = Disables 1 = Enables FLTWIDTH3[7] [30:24] Filtering width of GPB_INT[7] This value is valid when FLTSEL3 is 1. FLTEN3[6] [23] Filter Enable for GPB_INT[6]...
Page 207 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.29 GPIO Interrupt Control Registers (GPC0_INT_FLTCON0, R/W, Address = 0xE020_0818) GPC0_INT_FLTCON0 Description Initial State FLTEN4[3] [31] Filter Enable for GPC0_INT[3] 0 = Disables 1 = Enables FLTWIDTH4[3] [30:24] Filtering width of GPC0_INT[3] This value is valid when FLTSEL4 is 1. FLTEN4[2] [23] Filter Enable for GPC0_INT[2]...
Page 208 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.31 GPIO Interrupt Control Registers (GPC1_INT_FLTCON0, R/W, Address = 0xE020_0820) GPC1_INT_FLTCON0 Description Initial State FLTEN5[3] [31] Filter Enable for GPC1_INT[3] 0 = Disables 1 = Enables FLTWIDTH5[3] [30:24] Filtering width of GPC1_INT[3] This value is valid when FLTSEL5 is 1. FLTEN5[2] [23] Filter Enable for GPC1_INT[2]...
Page 209 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.33 GPIO Interrupt Control Registers (GPD0_INT_FLTCON0, R/W, Address = 0xE020_0828) GPD0_INT_FLTCON0 Description Initial State FLTEN6[3] [31] Filter Enable for GPD0_INT[3] 0 = Disables 1 = Enables FLTWIDTH6[3] [30:24] Filtering width of GPD0_INT[3] This value is valid when FLTSEL6 is 1. FLTEN6[2] [23] Filter Enable for GPD0_INT[2]...
Page 210 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.35 GPIO Interrupt Control Registers (GPD1_INT_FLTCON0, R/W, Address = 0xE020_0830) GPD1_INT_FLTCON0 Description Initial State FLTEN7[3] [31] Filter Enable for GPD1_INT[3] 0 = Disables 1 = Enables FLTWIDTH7[3] [30:24] Filtering width of GPD1_INT[3] This value is valid when FLTSEL7 is 1. FLTEN7[2] [23] Filter Enable for GPD1_INT[2]...
Page 211 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.37 GPIO Interrupt Control Registers (GPE0_INT_FLTCON0, R/W, Address = 0xE020_0838) GPE0_INT_FLTCON0 Description Initial State FLTEN8[3] [31] Filter Enable for GPE0_INT[3] 0 = Disables 1 = Enables FLTWIDTH8[3] [30:24] Filtering width of GPE0_INT[3] This value is valid when FLTSEL8 is 1. FLTEN8[2] [23] Filter Enable for GPE0_INT[2]...
Page 212 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.38 GPIO Interrupt Control Registers (GPE0_INT_FLTCON1, R/W, Address = 0xE020_083C) GPE0_INT_FLTCON1 Description Initial State FLTEN8[7] [31] Filter Enable for GPE0_INT[7] 0 = Disables 1 = Enables FLTWIDTH8[7] [30:24] Filtering width of GPE0_INT[7] This value is valid when FLTSEL8 is 1. FLTEN8[6] [23] Filter Enable for GPE0_INT[6]...
Page 213 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.39 GPIO Interrupt Control Registers (GPE1_INT_FLTCON0, R/W, Address = 0xE020_0840) GPE1_INT_FLTCON0 Description Initial State FLTEN9[3] [31] Filter Enable for GPE1_INT[3] 0 = Disables 1 = Enables FLTWIDTH9[3] [30:24] Filtering width of GPE1_INT[3] This value is valid when FLTSEL9 is 1. FLTEN9[2] [23] Filter Enable for GPE1_INT[2]...
Page 214 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.41 GPIO Interrupt Control Registers (GPF0_INT_FLTCON0, R/W, Address = 0xE020_0848) GPF0_INT_FLTCON0 Description Initial State FLTEN10[3] [31] Filter Enable for GPF0_INT[3] 0 = Disables 1 = Enables FLTWIDTH10[3] [30:24] Filtering width of GPF0_INT[3] This value is valid when FLTSEL10 is 1. FLTEN10[2] [23] Filter Enable for GPF0_INT[2]...
Page 215 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.42 GPIO Interrupt Control Registers (GPF0_INT_FLTCON1, R/W, Address = 0xE020_084C) GPF0_INT_FLTCON1 Description Initial State FLTEN10[7] [31] Filter Enable for GPF0_INT[7] 0 = Disables 1 = Enables FLTWIDTH10[7] [30:24] Filtering width of GPF0_INT[7] This value is valid when FLTSEL10 is 1. FLTEN10[6] [23] Filter Enable for GPF0_INT[6]...
Page 216 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.43 GPIO Interrupt Control Registers (GPF1_INT_FLTCON0, R/W, Address = 0xE020_0850) GPF1_INT_FLTCON0 Description Initial State FLTEN11[3] [31] Filter Enable for GPF1_INT[3] 0 = Disables 1 = Enables FLTWIDTH11[3] [30:24] Filtering width of GPF1_INT[3] This value is valid when FLTSEL11 is 1. FLTEN11[2] [23] Filter Enable for GPF1_INT[2]...
Page 217 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.44 GPIO Interrupt Control Registers (GPF1_INT_FLTCON1, R/W, Address = 0xE020_0854) GPF1_INT_FLTCON1 Description Initial State FLTEN11[7] [31] Filter Enable for GPF1_INT[7] 0 = Disables 1 = Enables FLTWIDTH11[7] [30:24] Filtering width of GPF1_INT[7] This value is valid when FLTSEL11 is 1. FLTEN11[6] [23] Filter Enable for GPF1_INT[6]...
Page 218 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.45 GPIO Interrupt Control Registers (GPF2_INT_FLTCON0, R/W, Address = 0xE020_0858) GPF2_INT_FLTCON0 Description Initial State FLTEN12[3] [31] Filter Enable for GPF2_INT[3] 0 = Disables 1 = Enables FLTWIDTH12[3] [30:24] Filtering width of GPF2_INT[3] This value is valid when FLTSEL12 is 1. FLTEN12[2] [23] Filter Enable for GPF2_INT[2]...
Page 219 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.46 GPIO Interrupt Control Registers (GPF2_INT_FLTCON1, R/W, Address = 0xE020_085C) GPF2_INT_FLTCON1 Description Initial State FLTEN12[7] [31] Filter Enable for GPF2_INT[7] 0 = Disables 1 = Enables FLTWIDTH12[7] [30:24] Filtering width of GPF2_INT[7] This value is valid when FLTSEL12 is 1. FLTEN12[6] [23] Filter Enable for GPF2_INT[6]...
Page 220 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.47 GPIO Interrupt Control Registers (GPF3_INT_FLTCON0, R/W, Address = 0xE020_0860) GPF3_INT_FLTCON0 Description Initial State FLTEN13[3] [31] Filter Enable for GPF3_INT[3] 0 = Disables 1 = Enables FLTWIDTH13[3] [30:24] Filtering width of GPF3_INT[3] This value is valid when FLTSEL13 is 1. FLTEN13[2] [23] Filter Enable for GPF3_INT[2]...
Page 221 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.49 GPIO Interrupt Control Registers (GPG0_INT_FLTCON0, R/W, Address = 0xE020_0868) GPG0_INT_FLTCON0 Description Initial State FLTEN14[3] [31] Filter Enable for GPG0_INT[3] 0 = Disables 1 = Enables FLTWIDTH14[3] [30:24] Filtering width of GPG0_INT[3] This value is valid when FLTSEL14 is 1. FLTEN14[2] [23] Filter Enable for GPG0_INT[2]...
Page 222 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.51 GPIO Interrupt Control Registers (GPG1_INT_FLTCON0, R/W, Address = 0xE020_0870) GPG1_INT_FLTCON0 Description Initial State FLTEN15[3] [31] Filter Enable for GPG1_INT[3] 0 = Disables 1 = Enables FLTWIDTH15[3] [30:24] Filtering width of GPG1_INT[3] This value is valid when FLTSEL15 is 1. FLTEN15[2] [23] Filter Enable for GPG1_INT[2]...
Page 223 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.53 GPIO Interrupt Control Registers (GPG2_INT_FLTCON0, R/W, Address = 0xE020_0878) GPG2_INT_FLTCON0 Description Initial State FLTEN16[3] [31] Filter Enable for GPG2_INT[3] 0 = Disables 1 = Enables FLTWIDTH16[3] [30:24] Filtering width of GPG2_INT[3] This value is valid when FLTSEL16 is 1. FLTEN16[2] [23] Filter Enable for GPG2_INT[2]...
Page 224 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.55 GPIO Interrupt Control Registers (GPG3_INT_FLTCON0, R/W, Address = 0xE020_0880) GPG3_INT_FLTCON0 Description Initial State FLTEN17[3] [31] Filter Enable for GPG3_INT[3] 0 = Disables 1 = Enables FLTWIDTH17[3] [30:24] Filtering width of GPG3_INT[3] This value is valid when FLTSEL17 is 1. FLTEN17[2] [23] Filter Enable for GPG3_INT[2]...
Page 225 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.57 GPIO Interrupt Control Registers (GPJ0_INT_FLTCON0, R/W, Address = 0xE020_0888) GPJ0_INT_FLTCON0 Description Initial State FLTEN18[3] [31] Filter Enable for GPJ0_INT[3] 0 = Disables 1 = Enables FLTWIDTH18[3] [30:24] Filtering width of GPJ0_INT[3] This value is valid when FLTSEL18 is 1. FLTEN18[2] [23] Filter Enable for GPJ0_INT[2]...
Page 226 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.58 GPIO Interrupt Control Registers (GPJ0_INT_FLTCON1, R/W, Address = 0xE020_088C) GPJ0_INT_FLTCON1 Description Initial State FLTEN18[7] [31] Filter Enable for GPJ0_INT[7] 0 = Disables 1 = Enables FLTWIDTH18[7] [30:24] Filtering width of GPJ0_INT[7] This value is valid when FLTSEL18 is 1. FLTEN18[6] [23] Filter Enable for GPJ0_INT[6]...
Page 227 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.59 GPIO Interrupt Control Registers (GPJ1_INT_FLTCON0, R/W, Address = 0xE020_0890) GPJ1_INT_FLTCON0 Description Initial State FLTEN19[3] [31] Filter Enable for GPJ1_INT[3] 0 = Disables 1 = Enables FLTWIDTH19[3] [30:24] Filtering width of GPJ1_INT[3] This value is valid when FLTSEL19 is 1. FLTEN19[2] [23] Filter Enable for GPJ1_INT[2]...
Page 228 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.61 GPIO Interrupt Control Registers (GPJ2_INT_FLTCON0, R/W, Address = 0xE020_0898) GPJ2_INT_FLTCON0 Description Initial State FLTEN20[3] [31] Filter Enable for GPJ2_INT[3] 0 = Disables 1 = Enables FLTWIDTH20[3] [30:24] Filtering width of GPJ2_INT[3] This value is valid when FLTSEL20 is 1. FLTEN20[2] [23] Filter Enable for GPJ2_INT[2]...
Page 229 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.62 GPIO Interrupt Control Registers (GPJ2_INT_FLTCON1, R/W, Address = 0xE020_089C) GPJ2_INT_FLTCON1 Description Initial State FLTEN20[7] [31] Filter Enable for GPJ2_INT[7] 0 = Disables 1 = Enables FLTWIDTH20[7] [30:24] Filtering width of GPJ2_INT[7] This value is valid when FLTSEL20 is 1. FLTEN20[6] [23] Filter Enable for GPJ2_INT[6]...
Page 230 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.63 GPIO Interrupt Control Registers (GPJ3_INT_FLTCON0, R/W, Address = 0xE020_08A0) GPJ3_INT_FLTCON0 Description Initial State FLTEN21[3] [31] Filter Enable for GPJ3_INT[3] 0 = Disables 1 = Enables FLTWIDTH21[3] [30:24] Filtering width of GPJ3_INT[3] This value is valid when FLTSEL21 is 1. FLTEN21[2] [23] Filter Enable for GPJ3_INT[2]...
Page 231 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.64 GPIO Interrupt Control Registers (GPJ3_INT_FLTCON1, R/W, Address = 0xE020_08A4) GPJ3_INT_FLTCON1 Description Initial State FLTEN21[7] [31] Filter Enable for GPJ3_INT[7] 0 = Disables 1 = Enables FLTWIDTH21[7] [30:24] Filtering width of GPJ3_INT[7] This value is valid when FLTSEL21 is 1. FLTEN21[6] [23] Filter Enable for GPJ3_INT[6]...
Page 232: Gpio Interrupt Control Registers
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.65 GPIO Interrupt Control Registers (GPJ4_INT_FLTCON0, R/W, Address = 0xE020_08A8) GPJ4_INT_FLTCON0 Description Initial State FLTEN22[3] [31] Filter Enable for GPJ4_INT[3] 0 = Disables 1 = Enables FLTWIDTH22[3] [30:24] Filtering width of GPJ4_INT[3] This value is valid when FLTSEL22 is 1. FLTEN22[2] [23] Filter Enable for GPJ4_INT[2]...
Page 233 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.67 GPIO Interrupt Control Registers (GPA0_INT_MASK, R/W, Address = 0xE020_0900) GPA0_INT_MASK Description Initial State Reserved [31:8] Reserved GPA0_INT_MASK[7] 0 = Enables Interrupt 1 = Masked GPA0_INT_MASK[6] 0 = Enables Interrupt 1 = Masked GPA0_INT_MASK[5] 0 = Enables Interrupt 1 = Masked GPA0_INT_MASK[4]...
Page 234 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.69 GPIO Interrupt Control Registers (GPB_INT_MASK, R/W, Address = 0xE020_0908) GPB_INT_MASK Description Initial State Reserved [31:8] Reserved GPB_INT_MASK[7] 0 = Enables Interrupt 1 = Masked GPB_INT_MASK[6] 0 = Enables Interrupt 1 = Masked GPB_INT_MASK[5] 0 = Enables Interrupt 1 = Masked GPB_INT_MASK[4]...
Page 235 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.70 GPIO Interrupt Control Registers (GPC0_INT_MASK, R/W, Address = 0xE020_090C) GPC0_INT_MASK Description Initial State Reserved [31:5] Reserved GPC0_INT_MASK[4] 0 = Enables Interrupt 1 = Masked GPC0_INT_MASK[3] 0 = Enables Interrupt 1 = Masked GPC0_INT_MASK[2] 0 = Enables Interrupt 1 = Masked GPC0_INT_MASK[1]...
Page 236 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.72 GPIO Interrupt Control Registers (GPD0_INT_MASK, R/W, Address = 0xE020_0914) GPD0_INT_MASK Description Initial State Reserved [31:4] Reserved GPD0_INT_MASK[3] 0 = Enables Interrupt 1 = Masked GPD0_INT_MASK[2] 0 = Enables Interrupt 1 = Masked GPD0_INT_MASK[1] 0 = Enables Interrupt 1 = Masked GPD0_INT_MASK[0]...
Page 237 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.74 GPIO Interrupt Control Registers (GPE0_INT_MASK, R/W, Address = 0xE020_091C) GPE0_INT_MASK Description Initial State Reserved [31:8] Reserved GPE0_INT_MASK[7] 0 = Enables Interrupt 1 = Masked GPE0_INT_MASK[6] 0 = Enables Interrupt 1 = Masked GPE0_INT_MASK[5] 0 = Enables Interrupt 1 = Masked GPE0_INT_MASK[4]...
Page 238 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.76 GPIO Interrupt Control Registers (GPF0_INT_MASK, R/W, Address = 0xE020_0924) GPF0_INT_MASK Description Initial State Reserved [31:8] Reserved GPF0_INT_MASK[7] 0 = Enables Interrupt 1 = Masked GPF0_INT_MASK[6] 0 = Enables Interrupt 1 = Masked GPF0_INT_MASK[5] 0 = Enables Interrupt 1 = Masked GPF0_INT_MASK[4]...
Page 239 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.78 GPIO Interrupt Control Registers (GPF2_INT_MASK, R/W, Address = 0xE020_092C) GPF2_INT_MASK Description Initial State Reserved [31:8] Reserved GPF2_INT_MASK[7] 0 = Enables Interrupt 1 = Masked GPF2_INT_MASK[6] 0 = Enables Interrupt 1 = Masked GPF2_INT_MASK[5] 0 = Enables Interrupt 1 = Masked GPF2_INT_MASK[4]...
Page 240 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.80 GPIO Interrupt Control Registers (GPG0_INT_MASK, R/W, Address = 0xE020_0934) GPG0_INT_MASK Description Initial State Reserved [31:7] Reserved GPG0_INT_MASK[6] 0 = Enables Interrupt 1 = Masked GPG0_INT_MASK[5] 0 = Enables Interrupt 1 = Masked GPG0_INT_MASK[4] 0 = Enables Interrupt 1 = Masked GPG0_INT_MASK[3]...
Page 241 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.82 GPIO Interrupt Control Registers (GPG2_INT_MASK, R/W, Address = 0xE020_093C) GPG2_INT_MASK Description Initial State Reserved [31:7] Reserved GPG2_INT_MASK[6] 0 = Enables Interrupt 1 = Masked GPG2_INT_MASK[5] 0 = Enables Interrupt 1 = Masked GPG2_INT_MASK[4] 0 = Enables Interrupt 1 = Masked GPG2_INT_MASK[3]...
Page 242 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.84 GPIO Interrupt Control Registers (GPJ0_INT_MASK, R/W, Address = 0xE020_0944) GPJ0_INT_MASK Description Initial State Reserved [31:8] Reserved GPJ0_INT_MASK[7] 0 = Enables Interrupt 1 = Masked GPJ0_INT_MASK[6] 0 = Enables Interrupt 1 = Masked GPJ0_INT_MASK[5] 0 = Enables Interrupt 1 = Masked GPJ0_INT_MASK[4]...
Page 243 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.86 GPIO Interrupt Control Registers (GPJ2_INT_MASK, R/W, Address = 0xE020_094C) GPJ2_INT_MASK Description Initial State Reserved [31:8] Reserved GPJ2_INT_MASK[7] 0 = Enables Interrupt 1 = Masked GPJ2_INT_MASK[6] 0 = Enables Interrupt 1 = Masked GPJ2_INT_MASK[5] 0 = Enables Interrupt 1 = Masked GPJ2_INT_MASK[4]...
Page 244 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.88 GPIO Interrupt Control Registers (GPJ4_INT_MASK, R/W, Address = 0xE020_0954) GPJ4_INT_MASK Description Initial State Reserved [31:5] Reserved GPJ4_INT_MASK[4] 0 = Enables Interrupt 1 = Masked GPJ4_INT_MASK[3] 0 = Enables Interrupt 1 = Masked GPJ4_INT_MASK[2] 0 = Enables Interrupt 1 = Masked GPJ4_INT_MASK[1]...
Page 245 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.89 GPIO Interrupt Control Registers (GPA0_INT_PEND, R/W, Address = 0xE020_0A00) GPA0_INT_PEND Description Initial State Reserved [31:8] Reserved GPA0_INT_PEND[7] 0 = Not occur 1 = Occur interrupt GPA0_INT_PEND[6] 0 = Not occur 1 = Occur interrupt GPA0_INT_PEND[5] 0 = Not occur 1 = Occur interrupt...
Page 246 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.91 GPIO Interrupt Control Registers (GPB_INT_PEND, R/W, Address = 0xE020_0A08) GPB_INT_PEND Description Initial State Reserved [31:8] Reserved GPB_INT_PEND[7] 0 = Not occur 1 = Occur interrupt GPB_INT_PEND[6] 0 = Not occur 1 = Occur interrupt GPB_INT_PEND[5] 0 = Not occur 1 = Occur interrupt...
Page 247 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.92 GPIO Interrupt Control Registers (GPC0_INT_PEND, R/W, Address = 0xE020_0A0C) GPC0_INT_PEND Description Initial State Reserved [31:5] Reserved GPC0_INT_PEND[4] 0 = Not occur 1 = Occur interrupt GPC0_INT_PEND[3] 0 = Not occur 1 = Occur interrupt GPC0_INT_PEND[2] 0 = Not occur 1 = Occur interrupt...
Page 248 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.94 GPIO Interrupt Control Registers (GPD0_INT_PEND, R/W, Address = 0xE020_0A14) GPD0_INT_PEND Description Initial State Reserved [31:4] Reserved GPD0_INT_PEND[3] 0 = Not occur 1 = Occur interrupt GPD0_INT_PEND[2] 0 = Not occur 1 = Occur interrupt GPD0_INT_PEND[1] 0 = Not occur 1 = Occur interrupt...
Page 249 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.96 GPIO Interrupt Control Registers (GPE0_INT_PEND, R/W, Address = 0xE020_0A1C) GPE0_INT_PEND Description Initial State Reserved [31:8] Reserved GPE0_INT_PEND[7] 0 = Not occur 1 = Occur interrupt GPE0_INT_PEND[6] 0 = Not occur 1 = Occur interrupt GPE0_INT_PEND[5] 0 = Not occur 1 = Occur interrupt...
Page 250 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.98 GPIO Interrupt Control Registers (GPF0_INT_PEND, R/W, Address = 0xE020_0A24) GPF0_INT_PEND Description Initial State Reserved [31:8] Reserved GPF0_INT_PEND[7] 0 = Not occur 1 = Occur interrupt GPF0_INT_PEND[6] 0 = Not occur 1 = Occur interrupt GPF0_INT_PEND[5] 0 = Not occur 1 = Occur interrupt...
Page 251 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.100 GPIO Interrupt Control Registers (GPF2_INT_PEND, R/W, Address = 0xE020_0A2C) GPF2_INT_PEND Description Initial State Reserved [31:8] Reserved GPF2_INT_PEND[7] 0 = Not occur 1 = Occur interrupt GPF2_INT_PEND[6] 0 = Not occur 1 = Occur interrupt GPF2_INT_PEND[5] 0 = Not occur 1 = Occur interrupt...
Page 252 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.102 GPIO Interrupt Control Registers (GPG0_INT_PEND, R/W, Address = 0xE020_0A34) GPG0_INT_PEND Description Initial State Reserved [31:7] Reserved GPG0_INT_PEND[6] 0 = Not occur 1 = Occur interrupt GPG0_INT_PEND[5] 0 = Not occur 1 = Occur interrupt GPG0_INT_PEND[4] 0 = Not occur 1 = Occur interrupt...
Page 253 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.104 GPIO Interrupt Control Registers (GPG2_INT_PEND, R/W, Address = 0xE020_0A3C) GPG2_INT_PEND Description Initial State Reserved [31:7] Reserved GPG2_INT_PEND[6] 0 = Not occur 1 = Occur interrupt GPG2_INT_PEND[5] 0 = Not occur 1 = Occur interrupt GPG2_INT_PEND[4] 0 = Not occur 1 = Occur interrupt...
Page 254 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.106 GPIO Interrupt Control Registers (GPJ0_INT_PEND, R/W, Address = 0xE020_0A44) GPJ0_INT_PEND Description Initial State Reserved [31:8] Reserved GPJ0_INT_PEND[7] 0 = Not occur 1 = Occur interrupt GPJ0_INT_PEND[6] 0 = Not occur 1 = Occur interrupt GPJ0_INT_PEND[5] 0 = Not occur 1 = Occur interrupt...
Page 255 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.108 GPIO Interrupt Control Registers (GPJ2_INT_PEND, R/W, Address = 0xE020_0A4C) GPJ2_INT_PEND Description Initial State Reserved [31:8] Reserved GPJ2_INT_PEND[7] 0 = Not occur 1 = Occur interrupt GPJ2_INT_PEND[6] 0 = Not occur 1 = Occur interrupt GPJ2_INT_PEND[5] 0 = Not occur 1 = Occur interrupt...
Page 256 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.110 GPIO Interrupt Control Registers (GPJ4_INT_PEND, R/W, Address = 0xE020_0A54) GPJ4_INT_PEND Description Initial State Reserved [31:5] Reserved GPJ4_INT_PEND[4] 0 = Not occur 1 = Occur interrupt GPJ4_INT_PEND[3] 0 = Not occur 1 = Occur interrupt GPJ4_INT_PEND[2] 0 = Not occur 1 = Occur interrupt...
Page 257 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.111 GPIO Interrupt Control Registers (GPIO_INT_GRPPRI, R/W, Address = 0xE020_0B00) GPIO_INT_GRPPRI Description Initial State Reserved [31:1] Reserved GPIO_INT_GRPPRI GPIO Interrupt groups priority rotate enable 0 = Not rotate (Fixed) 2.2.55.112 GPIO Interrupt Control Registers (GPIO_INT_PRIORITY, R/W, Address = 0xE020_0B04) GPIO_INT_PRIORITY Description Initial State...
Page 258 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPIO_INT_PRIORITY Description Initial State GPC1_INT_PRI GPC1_INT priority rotate enable 0 = Not rotate(Fixed) GPC0_INT_PRI GPC0_INT priority rotate enable 0 = Not rotate(Fixed) GPB_INT_PRI GPB_INT priority rotate enable 0 = Not rotate(Fixed) GPA1_INT_PRI GPA1_INT priority rotate enable 0 = Not rotate(Fixed) GPA0_INT_PRI GPA0_INT priority rotate enable...
Page 259 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.113 GPIO Interrupt Control Registers (GPIO_INT_SERVICE, R/W, Address = 0xE020_0B08) GPIO_INT_SERVICE Description Initial State Reserved [31:8] Reserved SVC_Group_Num [7:3] GPIO Interrupt Service group number (GPA0_INT ~ GPJ4_INT) Non_INT: 00000 == 0x0 GPA0_INT: 00001 == 0x1 GPA1_INT: 00010 == 0x2 GPB_INT: 00011 == 0x3 GPC0_INT: 00100 == 0x4...
Page 260 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.114 GPIO Interrupt Control Registers (GPIO_INT_SERVICE_PEND, R/W, Address = 0xE020_0B0C) GPIO_INT_SERVICE_PEND Description Initial State Reserved [31:8] Reserved SVC_PEND_Num [7:0] GPIO Interrupt Service Interrupt number (0 = Not occur , 1 = Occur interrupt) (0 ~ 7bit) 0bit: 0000_0001 == 0x1 1bit: 0000_0010 == 0x2 2bit: 0000_0100 == 0x4...
Page 261 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.115 GPIO Interrupt Control Registers (GPIO_INT_GRPFIXPRI, R/W, Address = 0xE020_0B10) GPIO_INT_GRPFIXPRI Description Initial State Reserved [31:5] Reserved Highest_GRP_NUM [4:0] Group number of the highest priority when fixed group priority mode: (GPA0_INT ~ GPJ4_INT) Non_INT: 00000 == 0x0 GPA0_INT: 00001 == 0x1 GPA1_INT: 00010 == 0x2 GPB_INT: 00011 == 0x3...
Page 262 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.117 GPIO Interrupt Control Registers (GPA1_INT_FIXPRI, R/W, Address = 0xE020_0B18) GPA1_INT_FIXPRI Description Initial State Reserved [31:3] Reserved Highest_EINT_NUM [2:0] Interrupt number of the highest priority in GPA1_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0.
Page 263 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.119 GPIO Interrupt Control Registers (GPC0_INT_FIXPRI, R/W, Address = 0xE020_0B20) GPC0_INT_FIXPRI Description Initial State Reserved [31:3] Reserved Highest_EINT_NUM [2:0] Interrupt number of the highest priority in GPC0_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0.
Page 264 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.122 GPIO Interrupt Control Registers (GPD1_INT_FIXPRI, R/W, Address = 0xE020_0B2C) GPD1_INT_FIXPRI Description Initial State Reserved [31:3] Reserved Highest_EINT_NUM [2:0] Interrupt number of the highest priority in GPD1_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0.
Page 265 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.125 GPIO Interrupt Control Registers (GPF0_INT_FIXPRI, R/W, Address = 0xE020_0B38) GPF0_INT_FIXPRI Description Initial State Reserved [31:3] Reserved Highest_EINT_NUM [2:0] Interrupt number of the highest priority in GPF0_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0.
Page 266 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.128 GPIO Interrupt Control Registers (GPF3_INT_FIXPRI, R/W, Address = 0xE020_0B44) GPF3_INT_FIXPRI Description Initial State Reserved [31:3] Reserved Highest_EINT_NUM [2:0] Interrupt number of the highest priority in GPF3_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0.
Page 267 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.131 GPIO Interrupt Control Registers (GPG2_INT_FIXPRI, R/W, Address = 0xE020_0B50) GPG2_INT_FIXPRI Description Initial State Reserved [31:3] Reserved Highest_EINT_NUM [2:0] Interrupt number of the highest priority in GPG2_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0.
Page 268 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.55.134 GPIO Interrupt Control Registers (GPJ1_INT_FIXPRI, R/W, Address = 0xE020_0B5C) GPJ1_INT_FIXPRI Description Initial State Reserved [31:3] Reserved Highest_EINT_NUM [2:0] Interrupt number of the highest priority in GPJ1_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0.
Page 269: Port Group Gph0 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.56 PORT GROUP GPH0 CONTROL REGISTER There are four control registers including GPH0CON, GPH0DAT, GPH0PUD and GPH0DRV in the Port Group GPH0 Control Registers. Group GPH0 is in alive area 2.2.56.1 Port Group GPH0 Control Register (GPH0CON, R/W, Address = 0xE020_0C00) GPH0CON Description Initial State...
Page 270 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.56.2 Port Group GPH0 Control Register (GPH0DAT, R/W, Address = 0xE020_0C04) GPH0DAT Description Initial State GPH0DAT[7:0] [7:0] When the port is configured as input port, the corresponding bit 0x00 is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 271: Port Group Gph1 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.57 PORT GROUP GPH1 CONTROL REGISTER There are four control registers including GPH1CON, GPH1DAT, GPH1PUD and GPH1DRV in the Port Group GPH1 Control Registers Group GPH1 is in alive area 2.2.57.1 Port Group GPH1 Control Register (GPH1CON, R/W, Address = 0xE020_0C20) GPH1CON Description Initial State...
Page 272 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.57.2 Port Group GPH1 Control Register (GPH1DAT, R/W, Address = 0xE020_0C24) GPH1DAT Description Initial State GPH1DAT[7:0] [7:0] When the port is configured as input port, the corresponding 0x00 bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 273: Port Group Gph2 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.58 PORT GROUP GPH2 CONTROL REGISTER There are four control registers, namely, GPH2CON, GPH2DAT, GPH2PUD and GPH2DRV in the Port Group GPH2 Control Registers. Group GPH2 is in alive area. 2.2.58.1 Port Group GPH2 Control Register (GPH2CON, R/W, Address = 0xE020_0C40) GPH2CON Description Initial State...
Page 274 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPH2CON Description Initial State 1111 = EXT_INT[22] GPH2CON[7] [31:28] 0000 = Input 0000 0001 = Output 0010 = Reserved 0011 = KP_COL[7] 0011 ~ 1110 = Reserved 1111 = EXT_INT[23] 2.2.58.2 Port Group GPH2 Control Register (GPH2DAT, R/W, Address = 0xE020_0C44) GPH2DAT Description Initial State...
Page 275: Port Group Gph3 Control Register
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.59 PORT GROUP GPH3 CONTROL REGISTER There are four control registers, namely, GPH3CON, GPH3DAT, GPH3PUD and GPH3DRV in the Port Group GPH3 Control Registers. Group GPH3 is alive area 2.2.59.1 Port Group GPH3 Control Register (GPH3CON, R/W, Address = 0xE020_0C60) GPH3CON Description Initial State...
Page 276 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT GPH3CON Description Initial State 1111 = EXT_INT[30] GPH3CON[7] [31:28] 0000 = Input 0000 0001 = Output 0010 = Reserved 0011 = KP_ROW[7] 0011 ~ 1110 = Reserved 1111 = EXT_INT[31] 2.2.59.2 Port Group GPH3 Control Register (GPH3DAT, R/W, Address = 0xE020_0C64) GPH3DAT Description Initial State...
Page 277: External Interrupt Control Registers
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60 EXTERNAL INTERRUPT CONTROL REGISTERS External Interrupt consists of 32 bits. EXT_INT[31:0] are used for wake-up source in Power down mode. In idle mode, all interrupts can be wake-up source; the other groups of external interrupts also can be the wake-up sources.
Page 278 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT EXT_INT_0_CON Description Initial State 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved [11] Reserved EXT_INT_0_CON[2] [10:8] Sets the signaling method of EXT_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered...
Page 279 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.2 External Interrupt Control Registers (EXT_INT_1_CON, R/W, Address = 0xE020_0E04) EXT_INT_1_CON Description Initial State Reserved [31] Reserved EXT_INT_1_CON[7] [30:28] Sets the signaling method of EXT_INT[15] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 280 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT EXT_INT_1_CON Description Initial State 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved EXT_INT_1_CON[1] [6:4] Sets the signaling method of EXT_INT[9] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 281 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.3 External Interrupt Control Registers (EXT_INT_2_CON, R/W, Address = 0xE020_0E08) EXT_INT_2_CON Description Initial State Reserved [31] Reserved EXT_INT_2_CON[7] [30:28] Sets the signaling method of EXT_INT[23] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 282 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT EXT_INT_2_CON Description Initial State 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved EXT_INT_2_CON[1] [6:4] Sets the signaling method of EXT_INT[17] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 283 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.4 External Interrupt Control Registers (EXT_INT_3_CON, R/W, Address = 0xE020_0E0C) EXT_INT_3_CON Description Initial State Reserved [31] Reserved EXT_INT_3_CON[7] [30:28] Sets the signaling method of EXT_INT[31] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 284 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT EXT_INT_3_CON Description Initial State 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Reserved EXT_INT_3_CON[1] [6:4] Sets the signaling method of EXT_INT[25] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved...
Page 285 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.5 External Interrupt Control Registers (EXT_INT_0_FLTCON0, R/W, Address = 0xE020_0E80) EXT_INT_0_FLTCON0 Description Initial State FLTEN_0[3] [31] Filter Enable for EXT_INT[3] 0 = Disables 1 = Enables FLTSEL_0[3] [30] Filter Selection for EXT_INT[3] 0 = Delay filter 1 = Digital filter (clock count) FLTWIDTH_0[3] [29:24]...
Page 286 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.6 External Interrupt Control Registers (EXT_INT_0_FLTCON1, R/W, Address = 0xE020_0E84) EXT_INT_0_FLTCON1 Description Initial State FLTEN_0[7] [31] Filter Enable for EXT_INT[7] 0 = Disables 1 = Enables FLTSEL_0[7] [30] Filter Selection for EXT_INT[7] 0 = Delay filter 1 = Digital filter(clock count) FLTWIDTH_0[7] [29:24]...
Page 287 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.7 External Interrupt Control Registers (EXT_INT_1_FLTCON0, R/W, Address = 0xE020_0E88) EXT_INT_1_FLTCON0 Description Initial State FLTEN_1[3] [31] Filter Enable for EXT_INT[11] 0 = Disables 1 = Enables FLTSEL_1[3] [30] Filter Selection for EXT_INT[11] 0 = Delay filter 1 = Digital filter (clock count) FLTWIDTH_1[3] [29:24]...
Page 288 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.8 External Interrupt Control Registers (EXT_INT_1_FLTCON1, R/W, Address = 0xE020_0E8C) EXT_INT_1_FLTCON1 Description Initial State FLTEN_1[7] [31] Filter Enable for EXT_INT[15] 0 = Disables 1 = Enables FLTSEL_1[7] [30] Filter Selection for EXT_INT[15] 0 = Delay filter 1 = Digital filter (clock count) FLTWIDTH_1[7] [29:24]...
Page 289 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.9 External Interrupt Control Registers (EXT_INT_2_FLTCON0, R/W, Address = 0xE020_0E90) EXT_INT_2_FLTCON0 Description Initial State FLTEN_2[3] [31] Filter Enable for EXT_INT[19] 0 = Disables 1 = Enables FLTSEL_2[3] [30] Filter Selection for EXT_INT[19] 0 = Delay filter 1 = Digital filter (clock count) FLTWIDTH_2[3] [29:24]...
Page 290 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.10 External Interrupt Control Registers (EXT_INT_2_FLTCON1, R/W, Address = 0xE020_0E94) EXT_INT_2_FLTCON1 Description Initial State FLTEN_2[7] [31] Filter Enable for EXT_INT[23] 0 = Disables 1 = Enables FLTSEL_2[7] [30] Filter Selection for EXT_INT[23] 0 = Delay filter 1 = Digital filter (clock count) FLTWIDTH_2[7] [29:24]...
Page 291 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.11 External Interrupt Control Registers (EXT_INT_3_FLTCON0, R/W, Address = 0xE020_0E98) EXT_INT_3_FLTCON0 Description Initial State FLTEN_3[3] [31] Filter Enable for EXT_INT[27] 0 = Disables 1 = Enables FLTSEL_3[3] [30] Filter Selection for EXT_INT[27] 0 = Delay filter 1 = Digital filter (clock count) FLTWIDTH_3[3] [29:24]...
Page 292 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.12 External Interrupt Control Registers (EXT_INT_3_FLTCON1, R/W, Address = 0xE020_0E9C) EXT_INT_3_FLTCON1 Description Initial State FLTEN_3[7] [31] Filter Enable for EXT_INT[31] 0 = Disables 1 = Enables FLTSEL_3[7] [30] Filter Selection for EXT_INT[31] 0 = Delay filter 1 = Digital filter(clock count) FLTWIDTH_3[7] [29:24]...
Page 293 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.13 External Interrupt Control Registers (EXT_INT_0_MASK, R/W, Address = 0xE020_0F00) EXT_INT_0_MASK Description Initial State Reserved [31:8] Reserved EXT_INT_0_MASK[7] 0 = Enables Interrupt 1 = Masked EXT_INT_0_MASK[6] 0 = Enables Interrupt 1 = Masked EXT_INT_0_MASK[5] 0 = Enables Interrupt 1 = Masked EXT_INT_0_MASK[4]...
Page 294 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.15 External Interrupt Control Registers (EXT_INT_2_MASK, R/W, Address = 0xE020_0F08) EXT_INT_2_MASK Description Initial State Reserved [31:8] Reserved EXT_INT_2_MASK[7] 0 = Enables Interrupt 1 = Masked EXT_INT_2_MASK[6] 0 = Enables Interrupt 1 = Masked EXT_INT_2_MASK[5] 0 = Enables Interrupt 1 = Masked EXT_INT_2_MASK[4]...
Page 295 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.17 External Interrupt Control Registers (EXT_INT_0_PEND, R/W, Address = 0xE020_0F40) EXT_INT_0_PEND Description Initial State Reserved [31:8] Reserved EXT_INT_0_PEND[7] 0 = Not occur 1 = Occur interrupt EXT_INT_0_PEND[6] 0 = Not occur 1 = Occur interrupt EXT_INT_0_PEND[5] 0 = Not occur 1 = Occur interrupt...
Page 296 S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.60.19 External Interrupt Control Registers (EXT_INT_2_PEND, R/W, Address = 0xE020_0F48) EXT_INT_2_PEND Description Initial State Reserved [31:8] Reserved EXT_INT_2_PEND[7] 0 = Not occur 1 = Occur interrupt EXT_INT_2_PEND[6] 0 = Not occur 1 = Occur interrupt EXT_INT_2_PEND[5] 0 = Not occur 1 = Occur interrupt...
Page 297: Extern Pin Configuration Registers In Power Down Mode
S5PC110_UM 2 GENERAL PURPOSE INPUT/ OUTPUT 2.2.61 EXTERN PIN CONFIGURATION REGISTERS IN POWER DOWN MODE This registers keep their values during power down mode 2.2.61.1 Extern Pin Configuration Registers in Power down Mode (PDNEN, R/W, Address = 0xE020_0F80) PDNEN Description Initial State Reserved [7:2]...
Page 298: Clock Controller
This chapter describes the clock management unit (CMU) supported by S5PC110. The system controller (SYSCON) manages CMU and power management unit (PMU) in S5PC110. 3.1 CLOCK DOMAINS S5PC110 consists of three clock domains, namely, main system (MSYS), display system (DSYS), and peripheral system (PSYS), as shown in Figure 3-1.
Page 299: Clock Declaration
S5PC110_UM 3 CLOCK CONTROLLER 3.2 CLOCK DECLARATION shows the classification of clocks in S5PC110. The top-level clocks in S5PC110 include: Figure 3-2 • Clocks from clock pads, that is, XRTCXTI, XXTI, XUSBXTI, and XHDMIXTI. • Clocks from CMU (for instance, ARMCLK, HCLK, PCLK, and so on.) •...
Page 300: Clocks From Cmu
VPLL uses SRCLK as input to generate 10MHz ~ 600MHz. This PLL generates 54MHz video clock. • USB OTG PHY uses XUSBXTI to generate 30MHz and 48MHz. In typical S5PC110 applications, • Cortex A8 and MSYS clock domain uses APLL (that is, ARMCLK, HCLK_MSYS, and PCLK_MSYS).
Page 301: Clock Relationship
S5PC110_UM 3 CLOCK CONTROLLER 3.3 CLOCK RELATIONSHIP Clocks have the following relationship: • MSYS clock domain − freq(ARMCLK) = freq(APLLCLK) / n, where n = 1 ~ 8 − freq(HCLK_MSYS) = freq(ARMCLK) / n, where n = 1 ~ 8 −...
Page 302: Recommended Pll Pms Value For Apll
S5PC110_UM 3 CLOCK CONTROLLER • − APLL can drive MSYS domain and DSYS domain. It can generate up to 1 GHz, 49:51 duty ratio. − MPLL can drive MSYS domain and DSYS domain. It supplies clock, up to 2 GHz and 40:60 duty ratio. −...
Page 303: Recommended Pll Pms Value For Mpll
S5PC110_UM 3 CLOCK CONTROLLER 3.3.2 RECOMMENDED PLL PMS VALUE FOR MPLL Table 3-2 MPLL PMS Value Target FOUT FVCO FOUT VSEL (MHz) (MHz) (MHz) (MHz) 1064.000 133.000 1328.000 166.000 1064.000 266.000 1332.000 333.000 1334.000 667.000 3.3.3 RECOMMENDED PLL PMS VALUE FOR EPLL Table 3-3 EPLL PMS Value Target FOUT...
Page 304: Recommended Pll Pms Value For Vpll
S5PC110_UM 3 CLOCK CONTROLLER 3.3.4 RECOMMENDED PLL PMS VALUE FOR VPLL Table 3-4 VPLL PMS Value Target FOUT FVCO FOUT VSEL (MHz) (MHz) (MHz) (MHz) 54.0000 432.000 54.000 108.000 432.000 108.000 74.2500 594.000 74.250 148.5000 594.000 148.500 222.7500 445.500 222.750 397.0000 396.000 396.000...
Page 305: Clock Generation
An external crystal clock is connected to the Figure 3-3 oscillation amplifier. The PLL converts low input frequency to high-frequency clock required by S5PC110. The clock generator block also includes a built-in logic to stabilize the clock frequency after each system reset, since clock takes time before stabilizing.
Page 306 SCLK _ HDMI 27M SCLK_ FIMC_ LCLK SCLK _ USBPHY 0 FIMC_LCLK SCLK _ USBPHY 1 SCLK _ HDMIPHY (1~16) SCLK M PLL MOUT FIMC _ LCLK SCLK E PLL SCLK V PLL Figure 3-3 S5PC110 Clock Generation Circuit 1...
Page 307: Table 3-5 Maximum Operating Frequency For Each Sub-Block
S5PC110_UM 3 CLOCK CONTROLLER Table 3-5 Maximum Operating Frequency for Each Sub-block Clock Max. Freq. Module Domain Cortex-A8, MFC, 3D TZIC0, TZIC1, TZIC2, TZIC3, VIC0, VIC1, VIC2, VIC3 200 MHz DMC0, DMC1 MSYS AXI_MSYS, AXI_MSFR, AXI_MEM 100 MHz IRAM, IROM, TZPC0 FIMC0, FIMC1, FIMC2, FIMD, DSIM, CSIS, JPEG, Rotator, 166 MHz VP, MIXER, TVENC, HDMI, MDMA, G2D...
Page 308: Clock Configuration Procedure
CLK_DIV0 [31:0] = target value0; Change the divider values for special clocks CLK_DIV1 [31:0] = target value1; CLK_DIV2 [31:0] = target value2; 3.5.1 CLOCK GATING S5PC110 can disable the clock operation of each IP if it is not required. This reduces dynamic power. 3-11...
Page 309: Special Clock Description
S5PC110_UM 3 CLOCK CONTROLLER 3.6 SPECIAL CLOCK DESCRIPTION 3.6.1 SPECIAL CLOCK TABLE Table 3-6 Special Clocks in S5PC110 Name Description Range Source SCLK_ONENAND ONE NAND operating ~166 MHz (A, M)PLL clock (SCLK_ONENAND) SCLK_G3D G3D core operating ~200 MHz (A, M, E, V)PLL...
Page 310: Table 3-7 I/O Clocks In S5Pc110
SCLK_USBPHY means USB PHY 48 MHz output clock. SCLK_HDMI27M means HDMI PHY (27 MHz reference clock) output. SCLK_HDMIPHY means HDMI PHY (PIXEL_CLKO) output clock. SCLKMPLL, SCLKEPLL, and SCLKVPLL mean output clock of MPLL, EPLL, and EPLL, respectively. Table 3-7 I/O Clocks in S5PC110 Name Type Description IOCLK_CFCON...
Page 311: Register Description
S5PC110_UM 3 CLOCK CONTROLLER 3.7 REGISTER DESCRIPTION System controller controls PLL, clock generator, the power management unit (PMU), and other system dependent units. This section describes how to control these parts using Special Functional Register (SFR) within the system controller. Do not change any reserved area. Changing value of Reserved area can lead to undefined behavior. 3.7.1 REGISTER MAP Register Address...
Page 312 S5PC110_UM 3 CLOCK CONTROLLER Register Address Description Reset Value CLK_SRC_MASK1 0xE010_0284 Clock source mask 1 0xFFFF_FFFF Reserved 0xE010_0288~ Reserved 0xE010_02FC CLK_DIV0 0xE010_0300 Set clock divider ratio 0 (System Clocks) 0x0000_0000 CLK_DIV1 0xE010_0304 Set clock divider ratio 1 (Multimedia) 0x0000_0000 CLK_DIV2 0xE010_0308 Set clock divider ratio 2 (Multimedia) 0x0000_0000...
Page 313 S5PC110_UM 3 CLOCK CONTROLLER Register Address Description Reset Value DCGIDX_MAP0 0xE010_3000 DCG index map 0 0xFFFF_FFFF DCGIDX_MAP1 0xE010_3004 DCG index map 1 0xFFFF_FFFF DCGIDX_MAP2 0xE010_3008 DCG index map 2 0xFFFF_FFFF Reserved 0xE010_300C~ Reserved 0xE010_301C DCGPERF_MAP0 0xE010_3020 DCG performance map 0 0xFFFF_FFFF DCGPERF_MAP1 0xE010_3024...
Page 314 The SFRs with address 0xE010_2XXX controls SW reset. The SFRs with address 0xE010_3XXX controls IEM block. The SFRs with address 0xE010_6XXX controls S5PC110 system. The SFRs withe address 0xE010_7XXX include miscellaneous registers. The SFRs with address 0xE010_8XXX controls the power management block.
Page 315: Pll Control Registers
S5PC110_UM 3 CLOCK CONTROLLER S5PC110 has four internal PLLs, namely, APLL, MPLL, EPLL, and VPLL. The four internal PLLs are controlled by the following eight special registers: 3.7.2 PLL CONTROL REGISTERS 3.7.2.1 PLL Control Registers (APLL_LOCK / MPLL_LOCK / EPLL_LOCK / VPLL_LOCK) •...
Page 316 S5PC110_UM 3 CLOCK CONTROLLER PLL_CON register controls the operation of each PLL. If ENABLE bit is set, the corresponding PLL generates output after PLL locking period. The MDIV, PDIV, and SDIV values control the output frequency of PLL. The PLL also generates the output frequency when MDIV, PDIV, and VSEL are changed.
Page 317 S5PC110_UM 3 CLOCK CONTROLLER APLL_CON1 Description Initial State AFC_ENB [31] Decides whether AFC is enabled or not. Active low. AFC selects adaptive frequency curve of VCO for wide range, high phase noise (or jitter) and fast lock time. (LOW: AFC is enabled, HIGH: AFC is disabled) Users should refer to on whether to use AFC for a 3.3.1...
Page 318 S5PC110_UM 3 CLOCK CONTROLLER 3.7.2.2 PLL Control Registers (MPLL_CON, R/W, Address = 0xE010_0108) MPLL_CON Description Initial State ENABLE [31] PLL enable control (0: disable, 1: enable) Reserved [30] Reserved LOCKED [29] PLL locking indication 0 = Unlocked 1 = Locked Read Only Reserved [28]...
Page 319 S5PC110_UM 3 CLOCK CONTROLLER 3.7.2.3 PLL Control Registers (EPLL_CON0/ EPLL_CON1, R/W, Address = 0xE010_0110/0xE010_0114) EPLL_CON0 Description Initial State ENABLE [31] PLL enable control (0: disable, 1: enable) Reserved [30] Reserved LOCKED [29] PLL locking indication 0 = Unlocked 1 = Locked Read Only Reserved [28]...
Page 320 S5PC110_UM 3 CLOCK CONTROLLER 460MHz ≤ FVCO ≤ 660MHz when VSEL=HIGH. FOUT: 12MHz ≤ FOUT ≤ 660MHz Refer to for recommended PMS values. 3.3.3 Recommended PLL PMS Value for EPLL EPLL should be turned on before entering following low-power modes. Deep idle, stop, deep stop, Caution: sleep mode.
Page 321 S5PC110_UM 3 CLOCK CONTROLLER 3.7.2.4 PLL Control Registers (VPLL_CON, R/W, Address = 0xE010_0120) VPLL_CON Description Initial State ENABLE [31] PLL enable control (0: disable, 1: enable) Reserved [30] Reserved LOCKED [29] PLL locking indication 0 = Unlocked 1 = Locked Read Only Reserved [28]...
Page 322: Clock Source Control Registers
3 CLOCK CONTROLLER 3.7.3 CLOCK SOURCE CONTROL REGISTERS S5PC110 has many clock sources, which include four PLL outputs, the external oscillator, the external clock, and other clock sources from GPIO. CLK_SRCn registers control the source clock of each clock divider.
Page 323 S5PC110_UM 3 CLOCK CONTROLLER 3.7.3.2 Clock Source Control Registers (CLK_SRC1, R/W, Address = 0xE010_0204) CLK_SRC1 Description Initial State Reserved [31:29] Reserved VPLLSRC_SEL [28] Control MUXVPLLSRC, which is the source clock of VPLL (0: Oscillator clock, 1: HDMI reference clock) CSIS_SEL [27:24] Control MUXCSIS, which is the source clock of CSIS (0000: XXTI, 0001: XusbXTI, 0010: SCLK_HDMI27M, 0011:...
Page 324 S5PC110_UM 3 CLOCK CONTROLLER 3.7.3.3 Clock Source Control Registers (CLK_SRC2, R/W, Address = 0xE010_0208) CLK_SRC2 Description Initial State Reserved [31:10] Reserved G2D_SEL [9:8] Control MUXG2D, which is the source clock of G2D core (00:SCLKA2M, 01:SCLKMPLL, 10:SCLKEPLL, 11:SCLKVPLL) Reserved [7:6] Reserved MFC_SEL [5:4] Control MUXMFC, which is the source clock of MFC core...
Page 325 S5PC110_UM 3 CLOCK CONTROLLER 3.7.3.4 Clock Source Control Registers (CLK_SRC3, R/W, Address = 0xE010_020C) CLK_SRC3 Description Initial State Reserved [31:24] Reserved 0x00 FIMC_LCLK_SEL [23:20] Control MUXFIMC_LCLK, which is the source clock of FIMC2 local clock (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved)
Page 326 S5PC110_UM 3 CLOCK CONTROLLER 3.7.3.5 Clock Source Control Registers (CLK_SRC4, R/W, Address = 0xE010_0210) CLK_SRC4 Description Initial State UART3_SEL [31:28] Control MUXUART3, which is the source clock of UART3 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) UART2_SEL...
Page 327 S5PC110_UM 3 CLOCK CONTROLLER 3.7.3.6 Clock Source Control Registers (CLK_SRC5, R/W, Address = 0xE010_0214) CLK_SRC5 Description Initial State Reserved [31:16] Reserved PWM_SEL [15:12] Control MUXPWM, which is the source clock of PWM (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Reserved...
Page 328 S5PC110_UM 3 CLOCK CONTROLLER 3.7.3.7 Clock Source Control Registers (CLK_SRC6, R/W, Address = 0xE010_0218) CLK_SRC6 Description Initial State Reserved [31:26] Reserved 0x00 DMC0_SEL [25:24] Control MUXDMC0, which is the source clock of DMC0 (00:SCLKA2M, 01:SCLKMPLL, 10:SCLKEPLL, 11:SCLKVPLL) PWI_SEL [23:20] Control MUXPWI, which is the source clock of PWI (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:...
Page 329 S5PC110_UM 3 CLOCK CONTROLLER 3.7.3.8 Clock Source Control Registers (CLK_SRC_MASK0, R/W, Address = 0xE010_0280) CLK_SRC_MASK0 Description Initial State Reserved [31:30] Reserved PWI_MASK [29] Mask output clock of MUXPWI (0: disable, 1: enable) Reserved [28] Reserved SPDIF_MASK [27] Mask output clock of MUXSPDIF (0: disable, 1: enable) AUDIO2_MASK [26] Mask output clock of MUXAUDIO2 (0: disable, 1: enable)
Page 330 S5PC110_UM 3 CLOCK CONTROLLER 3.7.3.9 Clock Source Control Registers (CLK_SRC_MASK1, Address = R/W, 0xE010_0284) CLK_SRC_MASK1 Description Initial State Reserved [31:7] Reserved 0x7FF_FFFF FIMC_LCLK_MASK Mask output clock of MUXFIMC_LCLK (0: disable, 1: enable) Should have same value as FIMC_LCLK_MASK Should have same value as FIMC_LCLK_MASK Reserved [1:0] Reserved...
Page 331: Clock Divider Control Register
3 CLOCK CONTROLLER 3.7.4 CLOCK DIVIDER CONTROL REGISTER S5PC110 has several clock dividers to support various operating clock frequency. The clock divider ratio can be controlled by CLK_DIV0, CLK_DIV1, 2, 3, 4, and 5. There are operating frequency limitations. The maximum operating frequency of SCLKAPLL, SCLKMPLL, SCLKA2M, HCLK_MSYS, and PCLK_MSYS are 800 MHz, 667 MHz, 400 MHz, 200 MHz, and 100 MHz, respectively.
Page 332 S5PC110_UM 3 CLOCK CONTROLLER 3.7.4.2 Clock Divider Control Register (CLK_DIV1, R/W, Address = 0xE010_0304) CLK_DIV1 Description Initial State CSIS_RATIO [31:28] DIVCSIS clock divider ratio, SCLK_CSIS = MOUTCSIS / (CSIS_RATIO + 1) Reserved [27:24] Reserved FIMD_RATIO [23:20] DIVFIMD clock divider ratio, SCLK_FIMD = MOUTFIMD / (FIMD_RATIO + 1) CAM1_RATIO [19:16]...
Page 333 S5PC110_UM 3 CLOCK CONTROLLER 3.7.4.4 Clock Divider Control Register (CLK_DIV3, R/W, Address = 0xE010_030C) CLK_DIV3 Description Initial State Reserved [31:24] Reserved 0x00 FIMC_LCLK_RATIO [23:20] DIVFIMC_LCLK clock divider ratio, SCLKFIMC_LCLK= MOUTFIMC_LCLK / (FIMC_LCLK_RATIO + 1) [19:16] Should have same value as FIMC_LCLK_RATIO [15:12] Should have same value as FIMC_LCLK_RATIO Reserved...
Page 334 S5PC110_UM 3 CLOCK CONTROLLER 3.7.4.6 Clock Divider Control Register (CLK_DIV5, R/W, Address = 0xE010_0314) CLK_DIV5 Description Initial State Reserved [31:12] Reserved PWM_RATIO [15:12] DIVPWM clock divider ratio, SCLK_PWM = MOUTPWM / (PWM_RATIO + 1) Reserved [11:8] Reserved SPI1_RATIO [7:4] DIVSPI1 clock divider ratio, SCLK_SPI1 = MOUTSPI1 / (SPI1_RATIO + 1) SPI0_RATIO [3:0]...
Page 335 S5PC110_UM 3 CLOCK CONTROLLER 3.7.4.8 Clock Divider Control Register (CLK_DIV7, R/W, Address = 0xE010_031C) CLK_DIV7 Description Initial State Reserved [31:15] Reserved DPM_RATIO [14:8] CLK_DPM clock divider ratio. Source of DIVDPM clock divider is PCLK for IEM_IEC. DPM_RATIO decides how often DPM channel increments for IEM_IEC.
Page 336: Clock Gating Control Register
S5PC110_UM 3 CLOCK CONTROLLER 3.7.5 CLOCK GATING CONTROL REGISTER There are two types of clock gating control registers for disable/enable operation, namely: • Clock gating control register by block • Clock gating register for by IP The above two registers are ANDed together to generate a final clock gating enable signal. As a result, if either of the two register field is turned OFF, the resulting clock is stopped.
Page 337 S5PC110_UM 3 CLOCK CONTROLLER CLK_GATE_IP0 Description Gated Clock Name Initial State PCLK_G2D Reserved [11:9] Reserved Reserved CLK_G3D Gating all clocks for G3D ACLK_G3D (0: mask, 1: pass) SCLK_G3D Reserved [7:6] Reserved Reserved CLK_IMEM Gating all clocks for IMEM ACLK_IMEM (0: mask, 1: pass) CLK_PDMA1 Gating all clocks for PDMA1 ACLK_PDMA1...
Page 338 S5PC110_UM 3 CLOCK CONTROLLER 3.7.5.3 Clock Gating Control Register (CLK_GATE_IP1, R/W, Address = 0xE010_0464) CLK_GATE_IP1 Description Gated Clock Name Initial State Reserved [31:29] Reserved CLK_NFCON [28] Gating all clocks for NFCON ACLK_NFCON (0: mask, 1: pass) Reserved [27] Reserved CLK_SROMC [26] Gating all clocks for SROM ACLK_SROMC...
Page 339 S5PC110_UM 3 CLOCK CONTROLLER 3.7.5.4 Clock Gating Control Register (CLK_GATE_IP2, R/W, Address = 0xE010_0468) CLK_GATE_IP2 Description Gated Clock Name Initial State CLK_TZIC3 [31] Gating all clocks for TZIC3 ACLK_TZIC3 (0: mask, 1: pass) CLK_TZIC2 [30] Gating all clocks for TZIC2 ACLK_TZIC2 (0: mask, 1: pass) CLK_TZIC1...
Page 340 S5PC110_UM 3 CLOCK CONTROLLER CLK_GATE_IP2 Description Gated Clock Name Initial State Reserved [7:2] Reserved 0x3F CLK_SDM Gating all clocks for SDM ACLK_SDM (0: mask, 1: pass) PCLK_SDM CLK_SECSS Gating all clocks for SECSS ACLK_SECSS (0: mask, 1: pass) Is should be guaranteed that S/W does not access IPs whose clock is gated. This can cause system Caution: failure.
Page 341 S5PC110_UM 3 CLOCK CONTROLLER 3.7.5.5 Clock Gating Control Register (CLK_GATE_IP3, R/W, Address = 0xE010_046C) CLK_GATE_IP3 Description Gated Clock Name Initial State Reserved [31] Reserved CLK_PCM2 [30] Gating all clocks for PCM2 PCLK_PCM2 (0: mask, 1: pass) SCLK_AUDIO2 CLK_PCM1 [29] Gating all clocks for PCM1 PCLK_PCM1 (0: mask, 1: pass) SCLK_AUDIO1...
Page 342 S5PC110_UM 3 CLOCK CONTROLLER CLK_GATE_IP3 Description Gated Clock Name Initial State CLK_SPI0 [12] Gating all clocks for SPI0 PCLK_SPI0 (0: mask, 1: pass) SCLK_SPI0 CLK_I2C_HDMI_PHY [11] Gating all clocks for I2C_HDMI_PHY PCLK_I2C_HDMI_PHY (0: mask, 1: pass) CLK_I2C_HDMI_DDC [10] Gating all clocks for I2C_HDMI_DDC PCLK_I2C_HDMI_DDC (0: mask, 1: pass) CLK_I2C2...
Page 343 S5PC110_UM 3 CLOCK CONTROLLER 3.7.5.6 Clock Gating Control Register (CLK_GATE_IP4, R/W, Address = 0xE010_0470) CLK_GATE_IP4 Description Gated Clock Name Initial State Reserved [31:9] Reserved 0x7F_FFFF CLK_TZPC3 Gating all clocks for TZPC3 PCLK_TZPC3 (0: mask, 1: pass) CLK_TZPC2 Gating all clocks for TZPC2 PCLK_TZPC2 (0: mask, 1: pass) CLK_TZPC1...
Page 344 S5PC110_UM 3 CLOCK CONTROLLER 3.7.5.7 Clock Gating Control Register (CLK_GATE_BLOCK, R/W, Address = 0xE010_0480) CLK_GATE_BLOCK Description Gated Clock Name Initial State Reserved [31:11] Reserved 0x1F_FFFF CLK_INTC [10] Gating all clocks for block-INTC ACLK_VIC0,1,2,3 (VIC0,1,2, TZIC0,1,2) ACLK_TZIC0,1,2,3 (0: mask, 1: pass) ACLK_AHB_ISFR CLK_HSMMC Gating all clocks for block-...
Page 345 S5PC110_UM 3 CLOCK CONTROLLER CLK_GATE_BLOCK Description Gated Clock Name Initial State CLK_TV Gating all clocks for block-TV (VP, ACLK_VP MIXER, TVENC) ACLK_MIXER (0: mask, 1: pass) ACLK_TVENC ACLK_AHB_TSFR ACLK_AXI_TSYS PCLK_HDMI PCLK_AXI_TSYS SCLK_MIXER SCLK_TVENC SCLK_DAC SCLK_PIXEL CLK_LCD Gating all clocks for block-LCD ACLK_FIMD (FIMD, G2D) ACLK_AHB_LSFR...
Page 346 S5PC110_UM 3 CLOCK CONTROLLER 3.7.5.8 Clock Gating Control Register (CLK_GATE_IP5, R/W, Address = 0xE010_0484) CLK_GATE_IP5 Description Gated Clock Name Initial State Reserved [31:30] Should be one for all bit CLK_JPEG [29] Gating all clocks for JPEG ACLK_JPEG (0: mask, 1: pass) Reserved [28:0] Should be one for all bit...
Page 347 S5PC110_UM 3 CLOCK CONTROLLER 3.7.5.9 Clock Gating Exceptions Some clock gating cells have exceptional conditions for gating clocks. This section summarizes this. SCLK_AUDIO0 is gated when all of the following register fields are cleared to LOW. This guarantees SCLK_AUDIO0 is running when any of the load is running. •...
Page 348: Clock Output Configuration Register
S5PC110_UM 3 CLOCK CONTROLLER 3.7.6 CLOCK OUTPUT CONFIGURATION REGISTER Internal clocks can be monitored through XCLKOUT PAD. CLK_OUT register selects an internal clock among PLL outputs, USBPHY output, HDMIPHY output, RTC, TICK, system bus clocks, ARMCLK, HPM clock and external OSCs.
Page 349: Figure 3-4 Clkout Waveform With Dclk Divider
S5PC110_UM 3 CLOCK CONTROLLER CLK_OUT Description Initial State DCLKSEL [3:1] Select DCLK source clock (000: XXTI, 001: XUSBXTI, 010: SCLK_HDMI27M, 011: SCLK_USBPHY0, 100: SCLK_USBPH1, 101: SCLK_HDMIPHY, 110: FOUTMPLL/2, 111: SCLKEPLL) DCLKEN Enable DCLK (0:disable, 1:enable) CLKOUT frequency = CLKIN (selected by CLKSEL) frequency / (DIVVAL+1) Figure 3-4 CLKOUT Waveform with DCLK Divider 3-52...
Page 350: Clock Divider Status Sfrs
S5PC110_UM 3 CLOCK CONTROLLER 3.7.7 CLOCK DIVIDER STATUS SFRS 3.7.7.1 Clock Divider Status SFRs (CLK_DIV_STAT0, R, Address = 0xE010_1000) CLK_DIV_STAT0 Description Initial State DIV_UART3 [31] DIVUART3 status (0: stable, 1: divider is changing) DIV_UART2 [30] DIVUART2 status (0: stable, 1: divider is changing) DIV_UART1 [29] DIVUART1 status (0: stable, 1: divider is changing)
Page 351 S5PC110_UM 3 CLOCK CONTROLLER 3.7.7.2 Clock Divider Status SFRs (CLK_DIV_STAT1, R, Address = 0xE010_1004) CLK_DIV_STAT1 Description Initial State Reserved [31:21] Reserved DIV_G2D [20] DIVG2D status (0: stable, 1: divider is changing) Reserved [19:18] Reserved DIV_DPM [17] DIVDPM status (0: stable, 1: divider is changing) DIV_DVSEM [16] DIVDVSEM status (0: stable, 1: divider is changing)
Page 352: Clock Mux Status Sfrs
S5PC110_UM 3 CLOCK CONTROLLER 3.7.8 CLOCK MUX STATUS SFRS 3.7.8.1 Clock MUX Status SFRs (CLK_MUX_STAT0, R, Address = 0xE010_1100) Clock MUX status registers show the status of glitch-free MUX logic. When CLK_SRCx SFR has been changed, it takes several clock cycles. Therefore, S/W should check the status of glitch-free MUX if the SFR values are applied.
Page 353 S5PC110_UM 3 CLOCK CONTROLLER 3.7.8.2 Clock MUX Status SFRs (CLK_MUX_STAT1, R, Address = 0xE010_1104) CLK_MUX_STAT1 Description Initial State DMC0_SEL [31:28] Selection signal status of MUXDMC0 (00x0:SCLKA2M, 00x1:SCLKMPLL, 010x:SCLKEPLL, 011x:SCLKVPLL, 1xxx: On changing) G2D_SEL [27:24] Selection signal status of MUXG2D (00x0:SCLKA2M, 00x1:SCLKMPLL, 010x:SCLKEPLL, 011x:SCLKVPLL, 1xxx: On changing) Reserved [23:19]...
Page 354: Other Sfrs
S5PC110_UM 3 CLOCK CONTROLLER 3.7.9 OTHER SFRS 3.7.9.1 Other SFRs (SWRESET, R/W, Address = 0xE010_2000) SWRESET Description Initial State Reserved [31:1] Reserved SWRESET Software reset (0: no effect, 1: reset) 3.7.10 IEM CONTROL SFRS 3.7.10.1 IEM Control SFRs (DCGIDX_MAP0, R/W, Address = 0xE010_3000) DCGIDX_MAP0 Description Initial State...
Page 355 S5PC110_UM 3 CLOCK CONTROLLER 3.7.10.4 IEM Control SFRs (DCGPERF_MAP0, R/W, Address = 0xE010_3020) DCGPERF_MAP0 Description Initial State DCGPERF_MAP0 [31:0] DCG performance map[31:0] 0xFFFF_FFFF 3.7.10.5 IEM Control SFRs (DCGPERF_MAP1, R/W, Address = 0xE010_3024) DCGPERF_MAP1 Description Initial State DCGPERF_MAP1 [31:0] DCG performance map[63:32] 0xFFFF_FFFF DCGPERF_MAP0~1 are mapped to IECCFGDCGPERFMAP[63:0] of IEM_IEC input port.
Page 356 S5PC110_UM 3 CLOCK CONTROLLER 3.7.10.7 IEM Control SFRs (FREQ_CPU, R/W, Address = 0xE010_3060) FREQ_CPU Description Initial State Reserved [31:24] Reserved 0x00 FREQ_CPU [23:0] Maximum frequency of CPU in kHz 0x00_0000 The register is related to IECCFGFREQCPU[23:0] of IEM_IEC input port. FREQ_CPU[23:0] is the maximum processor of frequency in KHz, and gives the clock frequency of the processor in KHz.
Page 357 S5PC110_UM 3 CLOCK CONTROLLER 3.7.10.9 IEM Control SFRs (DVSEMCLK_EN, R/W, Address = 0xE010_3080) DVSEMCLK_EN Description Initial State Reserved [31:1] Reserved 0x0000_0000 DVSEMCLK_EN DVS emulation clock enable The register is related to IECDVSEMCLKEN of IEM_IEC input port. DVSEMCLK_EN means the enable for advancing the PWM frame time slots when in DVS emulation mode.
Page 358 S5PC110_UM 3 CLOCK CONTROLLER 3.7.10.11 IEM Control SFRs • APLL_CON0_L8, R/W, Address = 0xE010_3100 • APLL_CON0_L7, R/W, Address = 0xE010_3104 • APLL_CON0_L6, R/W, Address = 0xE010_3108 • APLL_CON0_L5, R/W, Address = 0xE010_310C • APLL_CON0_L4, R/W, Address = 0xE010_3110 • APLL_CON0_L3, R/W, Address = 0xE010_3114 •...
Page 359 S5PC110_UM 3 CLOCK CONTROLLER 3.7.10.12 IEM Control SFRs • CLKDIV_IEM_L8, R/W, 0xE010_3200 • CLKDIV_IEM_L7, R/W, 0xE010_3204 • CLKDIV_IEM_L6, R/W, 0xE010_3208 • CLKDIV_IEM_L5, R/W, 0xE010_320C • CLKDIV_IEM_L4, R/W, 0xE010_3210 • CLKDIV_IEM_L3, R/W, 0xE010_3214 • CLKDIV_IEM_L2, R/W, 0xE010_3218 • CLKDIV_IEM_L1, R/W, 0xE010_321C CLKDIV_IEM_L1 ~ 8 Description Initial State...
Page 360: Miscellaneous Sfrs
S5PC110_UM 3 CLOCK CONTROLLER 3.7.11 MISCELLANEOUS SFRS 3.7.11.1 Miscellaneous SFRs (DISPLAY_CONTROL, R/W, Address = 0xE010_7008) DISPLAY_CONTROL Description Initial State Reserved [31:2] Reserved 0x0000_0000 DISPLAY_PATH_SEL [1:0] Display path selection 00: RGB=--- I80=FIMD ITU=FIMD 01: RGB=--- I80=--- ITU=FIMD 10: RGB=FIMD I80=FIMD ITU=FIMD 11: RGB=FIMD I80=FIMD ITU=FIMD 3.7.11.2 Miscellaneous SFRs (AUDIO_ENDIAN, R/W, Address = 0xE010_700C) AUDIO_ENDIAN...
Page 361: Power Management
IC (PMIC). Therefore, the internal power to S5PC110 is powered “off” except ALIVE block. (Note: RTC power to RTC and external power to I/O pad is still "on". If wakeup event occurs, S5PC110 is initialized by wakeup reset, as though power-on reset was asserted.) ‘Deep’...
Page 362: Functional Description Of Pmu
To control the switch cells, set registers NORMAL_CFG, IDLE_CFG, and STOP_CFG in SYSCON. Note that external power to S5PC110 is not "OFF". When power gating is applied, the states of normal F/Fs are lost, but the states of retention F/Fs are kept. Therefore, there can be two power-gating techniques, as listed below: •...
Page 363: Table 4-2 S5Pc110 Power Domains Of Internal Logic
S5PC110_UM 4 POWER MANAGEMENT Power “OFF” means that the power to S5PC110 is externally “OFF” using regulator or Power Management IC (PMIC). In S5PC110, SYSCON generates power control signal to regulator or PMIC. When power “OFF” is applied, the states of normal F/Fs and retention F/Fs are lost. Therefore, if you want to save some important data, you should move the data to external memory and restore it when wakeup event occurs.
Page 364: System Power Mode
4 POWER MANAGEMENT 4.3 SYSTEM POWER MODE 4.3.1 OVERVIEW According to the power saving schemes and features explained in , S5PC110 provides six power Section 4.3 modes, namely, NORMAL, IDLE, DEEP-IDLE, STOP, DEEP-STOP, and SLEEP. Power modes are summarized in Table 4-3.
Page 365 S5PC110_UM 4 POWER MANAGEMENT Table 4-3 Power Mode Summary Power NORMAL IDLE DEEP-IDLE STOP DEEP-STOP SLEEP Mode Run with Core Standby Power gating Standby Power gating Power off IEM1) Cortex- Retention/ Retention/ Run with IEM Power on Power on Power off Cache Power gating Power gating...
Page 366 S5PC110_UM 4 POWER MANAGEMENT There is second option in DEEP-IDLE mode for low-power MP3 playback, i.e., TOP block and SUB block is power-gated, but Audio block is still power ”ON”. This time is measured from wakeup event assertion to ARM reset de-assertion or ARM clock supply. That is, ARM runs the next instruction this time after wakeup event is asserted.
Page 367: Normal Mode
NOTE: Use Standby mode to disable CPU clock internally. The Standby mode is one of the power modes of ARM Cortex-A8. The clock to CPU is disabled to reduce switching current in ARM Cortex-A8. When S5PC110 enters IDLE mode, CPU clock is disabled using Standby mode, where application program is not running until wakeup event occurs.
Page 368 S5PC110_UM 4 POWER MANAGEMENT There are two wakeup techniques. First technique is applied to TOP domain and System Timer domain, whereas the other is applied to SUB domains (except System Timer domain). The first technique is as follows: The logic gates in TOP and System Timer domains are turned “ON” in two steps, and then memories are turned “ON”...
Page 369: Idle Mode
S5PC110_UM 4 POWER MANAGEMENT 4.3.3 IDLE MODE If Cortex-A8 is not required to operate, the clock for Cortex-A8 can be disabled internally. This saves the dynamic power consumption. To disable clock to Cortex-A8, execute a Wait-For-Interrupt instruction. The remaining parts of the chip (except state of Cortex-A8 core) keep their operating states in NORMAL, that is, the running modules are still running, clock-gated modules are still clock-gated, and power-gated modules are still power-gated.
Page 370 S5PC110_UM 4 POWER MANAGEMENT To enter the DEEP-IDLE mode, 1. Make sure all PLLs are running before entering low-power mode. This can be done by checking APLL_CON0, MPLL_CON, EPLL_CON0, VPLL_CON register. This step is required only when TOP_LOGIC field is set to 2'b01. 2.
Page 371: Stop Mode
S5PC110_UM 4 POWER MANAGEMENT 4.3.5 STOP MODE In STOP mode, clock to modules (except RTC module), PLLs, and unnecessary oscillators are selectively disabled to minimize dynamic power consumption. In this mode, Cortex-A8 Core enters into Standby mode. Therefore, current application program that is running in NORMAL mode stops in STOP mode and waits for wakeup event to resume.
Page 372 S5PC110_UM 4 POWER MANAGEMENT To exit STOP mode, wake up sources (For more information, refer to Then Section 4.6 "Wakeup Sources"). SYSCON performs the following sequence to exit from STOP mode. 1. Enable the OSC pads if disabled and wait for the OSC stabilization (around 1ms). 2.
Page 373: Deep-Stop Mode
S5PC110_UM 4 POWER MANAGEMENT 4.3.6 DEEP-STOP MODE In DEEP-STOP mode, Cortex-A8 Core is power-gated rather than clock-gated, and the remaining parts of the chip are power-gated (except RTC module). However, TOP domain can either be power-on or power-gated by setting TOP_LOGIC field of STOP_CFG register before entry into DEEP-STOP mode.
Page 374 S5PC110_UM 4 POWER MANAGEMENT 4. Let DRAMs exit from self-refresh mode. 4-14...
Page 375: Sleep Mode
S5PC110_UM 4 POWER MANAGEMENT 4.3.7 SLEEP MODE In SLEEP mode, all power domains are powered down (except ALIVE and RTC), all PLLs are disabled, and the oscillators (except RTC) are selectively disabled. To enter the SLEEP mode, 1. Set SLEEP_CFG based on the users' requirements. 2.
Page 376 S5PC110_UM 4 POWER MANAGEMENT Executing wfi instruction is a mandatory step when entering low-power mode. To make sure the Caution: processor does not ignore wfi instruction, it is recommended to make a loop statement around the wfi instruction. The loop repeatedly calls wfi instruciton until SYSCON_INT_DISABLE field of OTHERS register to become LOW, which indicates low-power mode entering sequence is completed.
Page 377: System Power Mode Transition
S5PC110_UM 4 POWER MANAGEMENT 4.4 SYSTEM POWER MODE TRANSITION shows the state transition diagram of power mode. Figure 4-1 System Reset SLEEP wake-up sources ARM command IDLE NORMAL SLEEP ARM command IDLE wake-up sources DEEP- DEEP- IDLE STOP STOP Figure 4-1 State Transition Diagram of Power Mode The wakeup sources described in are summarized in...
Page 378: Figure 4-2 Internal Operation During Power Mode Transition
S5PC110_UM 4 POWER MANAGEMENT NORMAL Write SFR IDLE/STOP PWR_MODE / STANDBYWFI Wait CLKST OPACK / Reset ARM STANDBYWFI DIS_ AR MC LK EN_ AR MCLK Mask ARMCLK IDLE Unmask ARMCLK TOP_IDLE STOP_ BU S RU N _ B US Disable BUS Enable BUS operation operation...
Page 379: Transition Entering/ Exiting Condition
S5PC110_UM 4 POWER MANAGEMENT 4.4.1 TRANSITION ENTERING/ EXITING CONDITION shows the Power Saving mode state and Entering or Exiting condition. As you can see, the entering Table 4-4 conditions are set by the main ARM CPU. Table 4-4 Power Saving Mode Entering/Exiting Condition Power Mode Enter Exit...
Page 380 S5PC110_UM 4 POWER MANAGEMENT 1. External Interrupt includes OneDRAM Interrupt 2. Depends on their interrupt mask bits. Power mode exit condition is met when one of various wakeup sources occurs. For more information on wakeup sources, refer to 4.6 "Wakeup Sources".
Page 381: Cortex-A8 Power Mode
S5PC110_UM 4 POWER MANAGEMENT 4.5 CORTEX-A8 POWER MODE 4.5.1 OVERVIEW Cortex-A8 has its own four power modes, namely, RUN, STANDBY, L2RETENTION, and POWER-OFF. In each power mode, power control of Cortex-A8 is done as follows: • In RUN mode, Core logic of Cortex-A8 is powered "ON" and clocked. The L2 cache of Cortex-A8 is power-on. •...
Page 382: Figure 4-3 Cortex-A8 Power Mode Transition Diagram
DEEP - STOP NORMAL SLEEP WFI instruction WFI instruction POWER - OFF L2RE TE NTION Wakeup event Wakeup event WFI instruction Wakeupevent STANDBY S5PC110 power mode IDLE, STOP Cortex - A8 power Figure 4-3 Cortex-A8 Power Mode Transition Diagram 4-22...
Page 383 S5PC110_UM 4 POWER MANAGEMENT Table 4-5 Cortex-A8 Power Control Cortex-A8 System Power Mode power mode NORMAL IDLE DEEP-IDLE STOP DEEP-STOP SLEEP transition Run with Power Cortex-A8 Core Standby Standby Power gating IEM1) gating By WFI Standby Standby N.A. N.A. command STANDBY By register setting and...
Page 384: State Save And Restore
S5PC110_UM 4 POWER MANAGEMENT 4.5.3 STATE SAVE AND RESTORE The current state of power-gated modules will be lost when their power turns ”OFF”. Therefore, before the modules are power-gated, their state should be saved, and restored after wakeup reset is asserted. In case of Cortex-A8, in DEEP-IDLE, DEEP-STOP, and SLEEP mode, the state of Cortex-A8 core will be lost, therefore the current states must be saved.
Page 385: Wakeup Sources
RTC clock and the generated clock from SYSCON as clock input. For System Timer to operate in DEEP-IDLE, STOP, and DEEP-STOP mode, power to System Timer is not gated. The wakeup event from System Timer will wake up S5PC110 from DEEP-IDLE, STOP, and DEEP-STOP mode. 4-25...
Page 386: External Power Control
S5PC110_UM 4 POWER MANAGEMENT 4.7 EXTERNAL POWER CONTROL shows the external power control summary. Table 4-7 Table 4-7 S5PC110 External Power Control DEEP-IDLE IDLE/ Block Controlled by NORMAL SLEEP / STOP / DEEP-IDLE DEEP-STOP Run / Keep operation Should be...
Page 387: Usb Otg Phy
S5PC110_UM 4 POWER MANAGEMENT 4.7.1 USB OTG PHY USB OTG PHY has three power modes, namely, Run, IDLE, and Suspend mode. • In Run mode, USB OTG PHY sends and receives data normally. • In IDLE mode, there is no data transaction to and from USB OTG PHY. However, the clock is still supplied to USB OTG PHY.
Page 388: Mipi D-Phy
S5PC110_UM 4 POWER MANAGEMENT 4.7.3 MIPI D-PHY MIPI D-PHY has three power modes, namely, Run, LP, and ULPS mode • In Run mode, MIPI D-PHY sends and receives data normally. • In LP and ULPS mode, all power MIPI D-PHY is off internally. In NORMAL mode, all three power modes can be used.
Page 389: Dac
4.7.4.1 Status of PLL after Wake-Up Event When the S5PC110 wakes up from STOP mode or SLEEP mode by an External Interrupt, a RTC alarm wakeup and other wakeup events, the PLL is turned “ON” automatically. However, the clock supply scheme is quite different.
Page 390: Adc I/O
S5PC110_UM 4 POWER MANAGEMENT 4.7.6 ADC I/O In DEEP-IDLE mode where TOP block is off, and DEEP-STOP mode where TOP block is off, the output port of normal I/O keeps its driving value before entering DEEP-IDLE/ DEEP-STOP mode. Normal I/O has output retention function, and it uses latch to keep its driving value.
Page 391: Internal Memory Control
S5PC110_UM 4 POWER MANAGEMENT 4.8 INTERNAL MEMORY CONTROL shows the internal memory power control summary. Table 4-9 Table 4-9 S5PC110 Internal Memory Control DEEP-IDLE IDLE/ Block Controlled by NORMAL SLEEP / STOP / DEEP-IDLE DEEP-STOP Stand-by Keep operation Run /...
Page 392: Rom
S5PC110_UM 4 POWER MANAGEMENT 4.8.2 ROM ROM has three power modes, namely, Run, Stand-by, and Power-down mode. • In Run mode, read access to ROM can be performed normally. • In Stand-by mode, chip selection to ROM is deactivated, so that there is no read access. •...
Page 393: Reset Control
4 POWER MANAGEMENT 4.9 RESET CONTROL 4.9.1 RESET TYPES S5PC110 has four types of resets and reset generator can place the system into one of five reset states. There are five reset states, namely: • Hardware Reset - The hardware reset is generated when XnRESET is driven to low. It is an uncompromised, ungated, and total reset that is used to drive S5PC110 to a known initial state.
Page 394 The crystal oscillator begins oscillation Figure 4-4 within several milliseconds after the power supply supplies enough power-level to the S5PC110. Internal PLLs are disabled after power-on reset is asserted. XnRESET signal should be released after the fully settle-down of the power supply-level.
Page 395 4.9.2.1 Watchdog Reset Watchdog reset is asserted when software fails to prevent the watchdog timer from timing out. In watchdog reset all units in S5PC110 (except some blocks listed in 4-10) are reset to their predefined reset states. The Table behavior after Watchdog reset is asserted, is the same as Hardware reset case.
Page 396 S5PC110_UM 4 POWER MANAGEMENT 4.9.2.3 Warm Reset Warm reset is asserted when XnWRESET is asserted to ‘0’. During the warm reset, the following actions occur: • All units (except some blocks listed in 4-10) go into their pre-defined reset state. Table •...
Page 397: Table 4-10 Register Initialization Due To Various Resets
S5PC110_UM 4 POWER MANAGEMENT Table 4-10 Register Initialization Due to Various Resets Block Register SYSCON (PMU) INFORM4~7, OM_STAT SYSCON (PMU) RST_STAT, PS_HOLD_CONTROL OSC_CON, PWR_CFG, EINT_WAKEUP_MASK, WAKEUP_MASK, PWR_MODE, NORMAL_CFG, IDLE_CFG, STOP_CFG, STOP_MEM_CFG, SLEEP_CFG, OSC_FREQ, OSC_STABLE, PWR_STABLE, MTC_STABLE, CLAMP_STABLE, SYSCON (PMU) WAKEUP_STAT, BLK_PWR_STAT, OTHERS, HDMI_CONTROL, USB_PHY_CONTROL, MIPI_DPHY_CONTROL, ADC_CONTROL, DAC_CONTROL, INFORM0~6...
Page 398: Register Description
S5PC110_UM 4 POWER MANAGEMENT 4.10 REGISTER DESCRIPTION Do not change any reserved area. Changing value of Reserved area can lead to undefined behavior. 4.10.1 REGISTER MAP Register Address Description Reset Value OSC_CON 0xE010_8000 Crystal oscillator control register 0x0000_0003 Reserved 0xE010_8004 ~ Reserved 0x0000_0000 0xE010_9FFC...
Page 399 S5PC110_UM 4 POWER MANAGEMENT Register Address Description Reset Value Reserved 0xE010_C118 ~ Reserved 0x0000_0000 0xE010_C1FC WAKEUP_STAT 0xE010_C200 Wakeup status registers 0x0000_0000 BLK_PWR_STAT 0xE010_C204 Block power status register 0x0000_00BF Reserved 0xE010_C208 ~ Reserved 0x0000_0000 0xE010_DFFC OTHERS 0xE010_E000 Others control register 0x0000_0000 Reserved 0xE010_E00C Reserved...
Page 400: Clock Control Register
4.10.2 CLOCK CONTROL REGISTER Clock control register enables and disables all oscillators for S5PC110. OSC_CON register control all oscillators for S5PC110. Each oscillator can be controlled independently. When oscillator pad is disabled, oscillation stops and no clock is generated further.
Page 401: Reset Control Register
S5PC110_UM 4 POWER MANAGEMENT 4.10.3 RESET CONTROL REGISTER 4.10.3.1 Reset Control Register (RST_STAT, R/W, Address = 0xE010_A000) RST_STAT Description Initial State Reserved [31:20] Reserved 0x000 DIDLE_WAKEUP [19] ARM reset from DEEP-IDLE DSTOP_WAKEUP [18] ARM reset from DEEP-STOP Reserved [17] Reserved SLEEP_WAKEUP [16] Reset by SLEEP mode wake-up...
Page 402: Power Management Register
S5PC110_UM 4 POWER MANAGEMENT 4.10.4 POWER MANAGEMENT REGISTER 4.10.4.1 Power Management Register (PWR_CFG, R/W, Address = 0xE010_C000) PWR_CFG Description Initial State Reserved [31:10] Reserved 0x00_0000 CFG_STANDBYWFI [9:8] Configure Cortex-A8 STANDBYWFI Determines what action is taken when the STANDBYWFI signal is activated by the Cortex-A8 00 = Ignore 01 = Enter IDLE mode 10 = Enter STOP mode...
Page 403 S5PC110_UM 4 POWER MANAGEMENT 4.10.4.3 Power Management Register (WAKEUP_MASK, R/W, Address = 0xE010_C008) WAKEUP_MASK Description Initial State Reserved [31:16] Reserved 0x0000 [15] Wake-up mask for HDMI-CEC (0: pass, 1: mask) [14] Wake-up mask for system timer (0: pass, 1: mask) [13] Wake-up mask for I2S within Audio sub-system (0: pass, 1: mask)
Page 404 S5PC110_UM 4 POWER MANAGEMENT 4.10.4.5 Power Management Register (NORMAL_CFG, R/W, Address = 0xE010_C010) NORMAL_CFG Description Initial State Reserved [31:21] Reserved 0x7FF IROM [20] Power gating control for I-ROM (0: LP mode (OFF), 1: Active mode (ON)) Reserved [19:8] Reserved 0xFFF AUDIO Power gating control for Audio sub-block (0: LP mode (OFF), 1: Active mode (ON))
Page 405 S5PC110_UM 4 POWER MANAGEMENT 4.10.4.6 Power Management Register (IDLE_CFG, R/W, Address = 0xE010_C020) IDLE_CFG Description Initial State TOP_LOGIC [31:30] Configure TOP logic state 01 = Retention 10 = ON Other: Reserved TOP_MEMORY [29:28] Configure TOP memory state 01 = Retention 10 = ON Other: Reserved ARM_L2CACHE...
Page 406 S5PC110_UM 4 POWER MANAGEMENT 4.10.4.7 Power Management Register (STOP_CFG, R/W, Address = 0xE010_C030) STOP_CFG Description Initial State TOP_LOGIC [31:30] Configure TOP logic state 01 = Retention 10 = ON Other: Reserved. Writing reserved values to registers can lead to unexpected behavior. When ARM_LOGIC is set to 2'b10 (STOP mode), this field should be 2'b10.
Page 407 S5PC110_UM 4 POWER MANAGEMENT 4.10.4.8 Power Management Register (STOP_MEM_CFG, R/W, Address = 0xE010_C034) STOP_MEM_CFG Description Initial State Reserved [31:9] Reserved 0x00_0000 ONENAND Memory retention control for ONENAND I/F (0: OFF, 1: Retention) MODEMIF Memory retention control for MODEM I/F (0: OFF, 1: Retention) Reserved Reserved USBOTG...
Page 408 S5PC110_UM 4 POWER MANAGEMENT 4.10.4.9 Power Management Register (SLEEP_CFG, R/W, Address = 0xE010_C040) SLEEP_CFG Description Initial State Reserved [31:2] Reserved 0x0000_0000 OSCUSB_EN Control USB X-tal Oscillator pad in SLEEP mode (0: disable, 1: enable) OSC_EN Control X-tal oscillator pad in SLEEP mode (0: Disable, 1: Enable) 4-48...
Page 409 S5PC110_UM 4 POWER MANAGEMENT 4.10.4.10 Power Management Register (OSC_FREQ, R/W, Address = 0xE010_C100) OSC_FREQ Description Initial State Reserved [31:4] Reserved 0x000_0000 OSC_FREQ_VALUE [3:0] Oscillator frequency scale counter ( OSC_FREQ_VALUE / oscillator_frequency > 200ns) 4.10.4.11 Power Management Register (OSC_STABLE, R/W, Address = 0xE010_C104) OSC_STABLE Description Initial State...
Page 410 S5PC110_UM 4 POWER MANAGEMENT MTC_STABLE counter indicates time required for power supplies to be stabilized when sub-block power is turned “ON”. Unless commented, use the default values. 4-50...
Page 411 S5PC110_UM 4 POWER MANAGEMENT 4.10.4.14 Power Management Register (CLAMP_STABLE, R/W, Address = 0xE010_C114) CLAMP_STABLE Description Initial State Reserved [31:26] Reserved 0x00 CLAMP_OFF_VALUE [25:16] Clamp OFF counter value 0x3FF Reserved [15:10] Reserved 0x00 CLAMP_ON_VALUE [9:0] Clamp ON counter value 0x3FF CLAMP_STABLE counter indicates time required for power supplies to be stabilized when Cortex processor power is turned “ON”...
Page 412 S5PC110_UM 4 POWER MANAGEMENT 4.10.4.16 Power Management Register (BLK_PWR_STAT, R, 0xE010_C204) BLK_PWR_STAT Description Initial State Reserved [31:8] Reserved AUDIO Audio block power ready (0: OFF, 1: ON) Reserved Reserved X-block power ready (0: OFF, 1: ON) T-block power ready (0: OFF, 1: ON) L-block power ready (0: OFF, 1: ON) G3D block power ready (0: OFF, 1: ON) F-block power ready (0: OFF, 1: ON)
Page 413: Misc Register
S5PC110_UM 4 POWER MANAGEMENT 4.10.5 MISC REGISTER 4.10.5.1 MISC Register (OTHERS, R/W, Address = 0xE010_E000) OTHERS Description Initial State RELEASE_RET_GPIO [31] RELEASE_RET_GPIO is retention control signal to normal I/O pad. If you want to disable RELEASE_RET_GPIO, set to 1. After RELEASE_RET_GPIO becomes OFF, this bit will be cleared to 0.
Page 414 S5PC110_UM 4 POWER MANAGEMENT OTHERS Description Initial State For more information on list of PADs belonging to MMC I/O pad, refer to Section 4.2 PIN SUMMARY of GPIO manual. RELEASE_RET_MMC_IO [29] RELEASE_RET_MMC_IO is retention control signal to MMC I/O pad. If you want to disable RELEASE_RET_MMC_IO, set to 1.
Page 415 S5PC110_UM 4 POWER MANAGEMENT OTHERS Description Initial State 1 = RELEASE_RET_UART_IO For more information on list of PADs belonging to UART I/O pad, refer to Section 4.2 PIN SUMMARY of GPIO manual. Reserved [27:18] Reserved 0x000 ARM_PRESETn_TYPE [17] ARM_PRESETn type selection 0 = Asserted when software reset is generated.
Page 416 S5PC110_UM 4 POWER MANAGEMENT 4.10.5.3 MISC Register (HDMI_CONTROL, R/W, Address = 0xE010_E804) HDMI_CONTROL Description Initial State Reserved [31:26] Reserved 0x00 DIV_RATIO [25:16] Clock divider ratio for HDMI 0x96 Reserved [15:1] Reserved 0x0000 ENABLE HDMI PHY enable (0: disable, 1: enable) 4.10.5.4 MISC Register (USB_PHY_CONTROL, R/W, Address = 0xE010_E80C) USB_PHY_CONTROL Description...
Page 417 S5PC110_UM 4 POWER MANAGEMENT 4.10.5.7 MISC Register (ADC_CONTROL, R/W, Address = 0xE010_E818) ADC_CONTROL Description Initial State Reserved [31:1] Reserved 0x0000_0000 DISABLE TS-ADC enable control (0: disable, 1: enable) 4.10.5.8 MISC Register (PS_HOLD_CONTROL, R/W, Address = 0xE010_E81C) PS_HOLD_CONTROL Description Initial State Reserved [31:12] Reserved...
Page 418: Intelligent Energy Management
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT INTELLIGENT ENERGY MANAGEMENT 5.1 OVERVIEW OF INTELLIGENT ENERGY MANAGEMENT The Intelligent Energy Management (IEM) solution is designed primarily for battery-powered equipment, where the major requirement is to have long battery life. The IEM solution is ideal for portable applications, for example, smartphones, feature phones, Personal Digital Assistants (PDA), hand held games consoles and portable media players.
Page 419: Key Features Of Intelligent Energy Management
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT The above listed components, which are part of the IEM system, co-operate with each other to optimize power consumption, without compromising on performance or responsiveness. Work flow of IEM system: • When the IEM software starts, software registers some kernel hooks with the OS. •...
Page 420: Block Diagram
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.1.2 BLOCK DIAGRAM AMBA APB Bus Maximum performance request Target Frequency Acknowledge Index ARM Core clock Clock Current Configuration Information HPM clock Management Frequency Index Unit Target Frequency Index Intelligent Power Current Frequency Index Energy Management Controller Unit...
Page 421: Functional Description Of Intelligent Energy Management
IEC the current performance level. This protocol is specified to support interfacing across asynchronous clock domains between high-speed PLL and clock-generator and low-speed voltage scaling hardware. The IEC provides an encoded performance index to S5PC110’s CMU and APC1 blocks.
Page 422 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT The IEC also includes a Design for Test (DFT) interface. This enables easier control over the scaling hardware during production testing of the SoC device. The IEC is an AMBA compliant, SoC peripheral that is developed, tested, and licensed by ARM Limited. The IEC features are as follows: •...
Page 423 5.2.1.2 DFT interface to control the target index outputs during SoC DFT. Advanced Power Controller S5PC110 uses Advanced Power Controller (APC1) from National Semiconductor for Dynamic Voltage Control. The APC1 is an advanced power controller designed for reuse in the AMBA-based designs with a standard APB slave interface to program registers.
Page 424 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT • Supports thermometer-encoded interface for a target performance level request and a current performance level update • Parameterized design supports up to eight performance levels • Supports sleep mode (retention level) power-down • Revision identification register to port software driver compliance •...
Page 425 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.2.1.4 Power Management Unit The Power Management Unit (PMU) in S5PC110X supports IEM features. The PMU provides configuration information to IEC, for example: • Fractional index map, indicating the fractional levels supported • Performance map, providing the mapping of the performance levels onto the clock frequencies supported by the CMU •...
Page 426: Iem System Operation
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.2.2 IEM SYSTEM OPERATION Loading and starting the software At an appropriate stage of system boot-up, the OS loads and initializes the modules that contain the IEM software: • On most platforms, the module loader automatically runs the initialization code for a module (if any) •...
Page 427 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.2.2.1 Handling System Events When an event occurs that might influence the optimum performance level, the OS calls the appropriate kernel hook in the IEM kernel: • The New Task hook is called whenever a new task is created. This hook generates a New Task system event for the new task that has just been created.
Page 428 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.2.2.2 Running the Fast Event Handlers The fast event handlers are run from the kernel hooks whenever a system event occurs. For each policy, the IEM kernel determines whether its fast event handler recognizes the system event. If so, the IEM kernel runs the fast event handler, passing it pointers to the IEM kernel data structures that include: •...
Page 429 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.2.2.3 Running the Standard Event Handlers The standard event handlers are run periodically by the IEM kernel. When the IEM kernel determines that it must run the standard event handlers, there are typically a number of outstanding system events in the event queue, that have not yet been processed by the standard event handlers.
Page 430: Iem Implementation And Driver Setting
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.3 IEM IMPLEMENTATION AND DRIVER SETTING 5.3.1 DEFINITION OF PERFORMANCE The maximum frequency of APLL is 2GHz. The expected frequency range of ARM Core is from 166MHz to 800MHz. AXI_MSYS bus, which is connected to ARM Core, works at 166MHz. In S5PC110X, CMU only uses clock divider to change performance.
Page 431: Hpm Structure And Closed-Loop Behavior
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.3.2 HPM STRUCTURE AND CLOSED-LOOP BEHAVIOR When IEM works with closed-loop, HPM and APC1 work as shown in Figure 5-4 Figure 5-5. integral_reg[20:0] ([20:14]=closedloop_vdd) rst_filterq | integral = hpm_targetclk_c ((integral > 22’h1F_C000) integral_reg + 21’h1F_C000 creset0 &...
Page 432: Figure 5-5 Iem Closed-Loop Control Flow In Apc1 Hpm Delay
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT clkdivcnt[5:0] apc_target_index[7:0] clkdivcnt == clock_div || 6’h00 APC_SLK_SMP (apc_target_index != apc_target_index_prv) apc_target_index_prv clkdivcnt APC_UNSHT_NOISE[5:4] noise_limit_int clock_div default 5’h00 5’h04 step_dir_int = 0 precnt = < cnt = Integral = 0 5’h10 step_upward = 0 {APC_VDDCHKD[7:0], APC_VDDCHK[3:0] mresult = 0 5’h1F...
Page 433: Figure 5-6 Hpm Delay Tap Structure In S5Pc110
5-6. Figure 5-6 HPM Delay Tap structure in S5PC110 HPM has a predelay module that includes 32 delay tap-like delay elements and a delayline module that includes 32 delay taps. To correlate with ARM core, 14-th tap should be selected with setting predelay_sel[2:0] of HPM 3’b000 when HPM clock ratio is equal to 1.
Page 434: Initialization Sequence
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.3.2.1 Calibration Code for Closed-loop In closed-loop mode, Calibration codes are used to control voltage level, while voltage values in open-loop mode. Calibration code stands for critical path delay of ARM core. In S5PC110X, 14-th tap output of HPM has the nearly same delay to the critical path of ARM core (when HPM clock ratio is equal to 1), which can be encoded to the delay code 5’hE.
Page 435: I/O Description
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.4 I/O DESCRIPTION Signal Description Type IEM_SCLK Bidirectional PWI clock IEM_SCLK dedicated IEM_SPWI Bidirectional PWI serial data IEM_SPWI dedicated NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals. 5-18...
Page 436: Register Description
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5 REGISTER DESCRIPTION 5.5.1 REGISTER MAP Register Address Description Reset Value IECDPCCR 0xE080_0000 DPC Control Register 0x000000E0 IECDVSEMSTR 0xE080_0004 DVS Emulation Slot Time Register 0x63 IECDPCTGTPERF 0xE080_0008 DPC Target Performance Register 0x80 IECDPCCRNTPERF 0xE080_000C DPC Current Performance Register System Dependent IECIMSC...
Page 437 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT Register Address Description Reset Value Register 1 IECITOP2 0xE080_0F24 Integration Test Output Read or Set 0x00 Register 2 IECITOP3 0xE080_0F28 Integration Test Output Read or Set 0x00 Register 3 IECITCR 0xE080_0F00 Integration Test Control Register IECPeriphID4 0xE080_0FD0 Peripheral Identification Register 4...
Page 438 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT Register Address Description Reset Value APC_SS_SRATE 0xE070_0058 APC Steady State Slew Rate Register 0x00 APC_IGAIN4 0xE070_005C Integrator’s Gain 4 Register 0x00 APC_IGAIN1 0xE070_0060 Integrator’s Gain 1 Register 0x00 APC_IGAIN2 0xE070_0064 Integrator’s Gain 2 Register 0x00 APC_IGAIN3 0xE070_0068 Integrator’s Gain 3 Register...
Page 439: Iec Related Registers
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2 IEC RELATED REGISTERS 5.5.2.1 DPC Control Register (IECDPCCR, R/W, Address = 0xE080_0000) IECDPCCR Description Initial State Reserved [31:8] Reserved, read undefined, do not modify. [7:5] When IECMAXPERF goes high, the IEC requests maximum Performance performance level which is decided by this register value.
Page 440 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.2 DVS Emulation Slot Time Register (IECDVSEMSTR, R/W, Address = 0xE080_0004) IECDVSEMSTR Description Initial State Reserved [31:10] Reserved, read undefined, do not modify. Slot time [9:0] The time in μs for each slot of a PWM frame. This is reset 0x63 to 0x63.
Page 441 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.6 Raw Interrupt Status Register (IECRIS, R, Address = 0xE080_0014) IECRIS Description Initial State Reserved [31:2] Reserved, read undefined, do not modify. CPU Sleep Interrupt Returns the raw interrupt state prior to masking of the Status (CSRIS) IECCPUSLPINT interrupt.
Page 442 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.10 DPM Frequency Register (IECDPMFREQ, R, Address = 0xE080_0024) IECDPMFREQ Description Initial State Reserved [31:24] Reserved, read undefined, do not modify. DPM Frequency (DPMF) [23:0] The DPM frequency in kHz. From PMU 5.5.2.11 Configuration Fractional Index Map00 Register (IECCFGDCGIDXMAP00, R, Address = 0xE080_0040) IECCFGDCGIDXMAP00 Description...
Page 443 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.17 DPM Command Register (IECDPMCR, R/W, Address = 0xE080_0100) IECDPMCR Description Initial State Reserved [31:12] Reserved, read undefined, do not modify. DPMCH3CMD [11:8] DPM Channel 3 command. DPMCH2CMD [7:4] DPM Channel 2 command. DPMCH1CMD [3:0] DPM Channel 1 command.
Page 444 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.22 DPM Channel Registers (IECDPM2LO, R, Address = 0xE080_0188) IECDPM2LO Description Initial State IECDPM2LO [31:0] Low 32-bit of DPM channel 2. 0x00000000 The reset value is 0x00000000. 5.5.2.23 DPM Channel Registers (IECDPM2HI, R, Address = 0xE080_018C) IECDPM2HI Description Initial State...
Page 445 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.26 IEC Integration Test Control Register (IECITCR, R/W, Address = 0xE080_0F00) IECITCR Description Initial State [31:3] Reserved. Unpredictable when read. Should be written as zero. DPM Counter Test Enable or disable test mode for all DPM counters. 0 = DPM counter test mode disabled, also the reset value.
Page 446 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.27 IEC Integration Test Input Read or Set Registers (IECITIP1, R/W, Address = 0xE080_0F10) IECITIP1 Description Initial State [31:5] Reserved. Unpredictable when read. Should be written as zero. IECSYNCMODEACK Intra-chip input. Writes to this bit, set the value to be driven onto the input IECSYNCMODEACK, in the integration test mode.
Page 447 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.28 IEC Integration Test Input Read or Set Registers (IECITIP1, R/W, Address = 0xE080_0F14) IECITIP2 Description Initial State [31:8] Reserved, read undefined, do not modify. IECCRNTDCGIDX [7:0] Intra-chip input. 0x00 Writes to these bits set the value to be driven onto the inputs IECCRNTDCGIDX[7:0], in the integration test mode.
Page 448 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.31 Integration Test Output Read or Set Registers (IECITOP2, R/W, Address = 0xE080_0F24) IECITOP2 Description Initial State Reserved [31:8] Reserved, read undefined, do not modify. IECTGTDCGIDX [7:0] Intra-chip outputs. Writes to these bits set the value to be 0x00 driven onto the IECTGTDCGIDX [7:0] outputs in integration test mode.
Page 449 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.36 Peripheral Identification Register 3 (IECPeriphID3, R, Address = 0xE080_0FEC) IECPeriphID3 Description Initial State Reserved [31:8] Reserved, read undefined, do not modify. Configuration 1 [7:0] Number of DPC levels. 0x08 These bits read back as 0x08. 5.5.2.37 Peripheral Identification Register 4 (IECPeriphID4, R, Address = 0xE080_0FD0) IECPeriphID4 Description...
Page 450 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.2.41 IEC Identification Register 0 (IECID0, R, Address = 0xE080_0FF0) IECID0 Description Initial State [31:8] Reserved, read undefined, do not modify. IECID0 [7:0] These bits read back as 0x0D 0x0D 5.5.2.42 IEC Identification Register 1 (IECID1, R, Address = 0xE080_0FF4) IECID1 Description Initial State...
Page 451: Apc1 Related Registers
S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3 APC1 RELATED REGISTERS 5.5.3.1 PWI Command Register (APC_PWICMD, R/W, Address = 0xE070_0000) APC_PWICMD Description Initial State PWI Slave Register Address [7:4] PWI slave Register address of the read and write register. PWI Slave Command [3:0] PWI slave command: 4’b0000 = Reset...
Page 452 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.4 APC Control Register (APC_CONTROL, R/W, Address = 0xE070_0010) APC_CONTROL Description Initial State APC_HPM_AUTH_SET HPM is set to the ring oscillator mode for a random PC used in the authentication sequence. APC_PWRSV_EN Enables the power save mode. On setting this bit: * the apc_refclk_req signal is deasserted when the apc_refclk_c clock signal is not required * the CMU can gate off the clock signal to save the...
Page 453 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.6 Minimum Limit Register (APC_MINVDD_LIMIT, R/W, Address = 0xE070_0018) APC_MINVDD_LIMIT Description Initial State Reserved Read undefined. Write as zero. Minimum core voltage [6:0] Minimum SoC operating core voltage. 0x00 5.5.3.7 VDD Check Register (APC_VDDCHK, R/W, Address = 0xE070_001C) APC_VDDCHK Description Initial State...
Page 454 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.11 APC Interrupt Status Register (APC_ISTATUS, R, Address = 0xE070_002C) APC_ISTATUS Description Initial State Reserved Read undefined. APB Write Discard When the PWI command is active in the APC1, the new PWI commands issued by the host are discarded. This discarded status is reflected in this bit.
Page 455 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.13 APC Undershoot Threshold and Noise Limit Register (APC_UNSHT_NOISE, R/W, Address = 0xE070_0034) APC_UNSHT_NOISE Description Initial State Reserved [7:6] Read undefined. Write as zero. Noise Limit for VDDOK [5:4] Noise limit for the VDDOK generation due to the power supply regulation errors.
Page 456 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.16 PWI Clock Division Register (APC_CLKDIV_PWICLK, R/W, Address = 0xE070_0040) APC_CLKDIV_PWICLK Description Initial State Reserved [7:4] Read undefined. Write as zero. Programmable Clock [3:0] Programmable division to theapc_refclk_c clock frequency Division for the PWI clock. The clock division is equal to 2 * (APC_CLKDIV_PWICLK + 1).
Page 457 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.20 Integrator’s Gain Registers (APC_IGAIN1, R/W, Address = 0xE070_0060) APC_IGAIN1 Description Initial State Reserved [7:4] Read undefined. Write as zero. Gain 1 [3:0] Default gain term for the dynamic compensator. The programmable values for this gain term are one to ten. Rest of the values are treated as zero in the closed-loop AVS operations.
Page 458 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.24 Integration Test Control Register (APC_ITSTCTRL, R/W, Address = 0xE070_006C) APC_ITSTCTRL Description Initial State Reserved [7:2] Undefined. Write as zero. IT_OPEN Integration test output enable. The reset value is zero. 1 = APC1 is in integration test mode. 0 = APC1 is in normal mode.
Page 459 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.26 Integration Test Input Read or Set Registers (APC_ITSTIP2, R/W, Address = 0xE070_0074) APC_ITSTIP2 Description Initial State Reserved [7:N] Read undefined. Write as zero. APC_TARGET_INDEX [N-1:0] In integration test mode: 0x00 write drives the apc_target_index inputs to the design •...
Page 460 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.27 Integration Test Output Read or Set Registers (APC_ITSTOP1, R/W, Address = 0xE070_0078) APC_ITSTOP1 Description Initial State APC_PREDELAY [7:5] In integration test mode: _SEL[2:0] write drives the apc_predelay_selprimary outputs • read returns the register content. •...
Page 461 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.28 Integration Test Output Read or Set Registers (APC_ITSTOP2, R/W, Address = 0xE070_007C) APC_ITSTOP2 Description Initial State Reserved [7:N] Read undefined. Write as zero. APC_CURRENT_INDEX [N-1:0] In integration test mode: 0x00 write drives the apc_current_index primary outputs •...
Page 462 S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT 5.5.3.30 Voltage Information Registers APC1 has two types of voltage information registers. Ones are for closed-loop control, and the others are for open-loop control. Registers for closed-loop control give delay information, while registers for open-loop control give direct voltage information.
Page 463 S5PC110_UM 5.5.3.31 Retention VDD Registers (APC_RET_VDD, R/W, Address = 0xE070_00C0) APC_RET_VDD Description Initial State Reserved Read undefined. Write as zero. Retention VDD [6:0] The retention voltage level for performance level zero. 0x00 5.5.3.32 Debug Performance Registers (APC_DBG_DLYCODE, R, Address = 0xE070_00E0) APC_DBG_DLYCODE Description Initial State...
Page 464: Booting Sequence
BOOTING SEQUENCE 6.1 OVERVIEW OF BOOTING SEQUENCE S5PC110 consists of 64KB ROM and 96KB SRAM as internal memory. For booting, internal 64KB ROM and internal 96KB SRAM regions can be used. S5PC110 boots from internal ROM to enable secure booting, which ensures that the image cannot be altered by unauthorized users.
Page 465: Figure 6-1 Block Diagram Of Booting Time Operation
S5PC110_UM 6 BOOTING SEQUENCE shows the block diagram of booting time operation. Figure 6-1 Figure 6-1 Block Diagram of Booting Time Operation • The iROM code is placed in internal 64KB ROM. It initializes basic system functions such as clock, stack, and heap.
Page 466: Scenario Description
S5PC110_UM 6 BOOTING SEQUENCE 6.2 SCENARIO DESCRIPTION 6.2.1 RESET STATUS There are several scenarios for system reset such as hardware reset, watchdog reset, software reset, and wake up from power down modes. For each scenario, the mandatory functions are summarized in Table 6-1 Table 6-1 Functions Needed for Various Reset Status...
Page 467: Booting Sequence Example
S5PC110_UM 6 BOOTING SEQUENCE 6.2.2 BOOTING SEQUENCE EXAMPLE shows the flow chart related to total booting code sequence. Figure 6-2 Figure 6-2 Total Booting Code Sequence Flow Chart...
Page 468 7. Jump to OS code in DRAM (0x2000_0000 or 0x4000_0000) The booting sequence in DRAM is as follows: 1. If S5PC110 is powered on from SLEEP, DEEP_STOP, or DEEP_IDLE modes, then restore the previous state. 2. Jump to OS code.
Page 469: Fixed Pll And Clock Setting
S5PC110_UM 6 BOOTING SEQUENCE 6.2.3 FIXED PLL AND CLOCK SETTING To speed up first boot loader’s operation, the first boot loader initializes the PLL with fixed value. Fixed PLL setting is as follows: (SDIV-1) • APLL: M=200, P=6, S=1 FOUT = (MDIV X FIN )/ (PDIV X 2 )) = 800MHz SDIV •...
Page 470: Om Pin Configuration
S5PC110_UM 6 BOOTING SEQUENCE 6.2.4 OM PIN CONFIGURATION shows the booting option that can be set by OM pins. Table 6-3 Table 6-3 OM Pin Setting for Various Booting Option OM[5] OM[4] OM[3] OM[2] OM[1] OM[0] OM[5] OM[4] OM[3] OM[2] OM[1] OM[0] Boot...
Page 471 S5PC110_UM 6 BOOTING SEQUENCE OM[5] OM[4] OM[3] OM[2] OM[1] OM[0] OM[5] OM[4] OM[3] OM[2] OM[1] OM[0] 1'b1 X-TAL(USB) 1'b0 X-TAL 1'b1 OnenandDemux(Audi) 1'b1 X-TAL(USB) 1'b0 X-TAL 1'b0 SD/MMC 1'b1 X-TAL(USB) 1'b1 1'b0 X-TAL 1'b1 eMMC(4-bit) 1'b1 X-TAL(USB) NOTE: The first boot loader tries to negotiate UART first. If it fails, then it tries to drive the USB device. Hence, you have to disconnect the UART device if you want to boot using USB device.
Page 472: Secure Booting
‘validate’ itself.” In S5PC110, the root of trust is implemented by iROM code in internal ROM. Therefore it cannot be modified by unauthorized users. The hardware design proves the integrity of iROM code. On the other hand, the first boot loader, the second boot loader and OS images are stored in external memory devices.
Page 473: Figure 6-3 Secure Booting Diagram
S5PC110_UM 6 BOOTING SEQUENCE Figure 6-3 Secure Booting Diagram 6-10...
Page 474 Section 3...
Page 475 Table of Contents Bus Configuration ..................1-2 1.1 Overview of Bus Configuration ........................ 1-2 1.1.1 AXI Interconnect ..........................1-2 1.2 Register Description..........................1-6 1.2.1 Register Map ............................ 1-6 1.2.2 Synchronizer Configuration Register (ASYNC_CONFIG0~10, R/W)..........1-7 Coresight.....................2-1 2.1 Coresight System Overview........................2-1 2.1.1 About Coresight Systems Generals ....................
Page 476 DAP Connections Inside a SoC Cross Triggering ................2-3 Figure 2-2 S5PC110 Coresight Structure ......................2-4 Figure 2-3 Debugger Register Map of S5PC110 ....................2-5 Figure 2-4 Structure of the Coresight DAP Components................... 2-8 Figure 2-5 ETB Block Diagram ECT (CTI + CTM) ..................... 2-9 Figure 2-6 Coresight CTI and CTM Block Diagram ..................
Page 477 List of Tables Table Title Page Number Number Table 2-1 Authentication Signal Rule......................... 2-6 Table 3-1 TZPC Table............................3-3 Table 3-2 TZPC Transfer Attribute........................3-4 Table 3-3 TZPC Registers..........................3-5...
Page 478: Bus Configuration
1.1 OVERVIEW OF BUS CONFIGURATION This chapter describes the bus configuration in S5PC110. 1.1.1 AXI INTERCONNECT S5PC110 consists of 12 high-performance AXI interconnect. The role of AXI interconnect is to interconnect bus masters to bus slaves. 1.1.1.1 Key Features of AXI Interconnect The key features of AXI interconnect include: •...
Page 479 S5PC110_UM 1 BUS CONFIGURATION Figure 1-1 Example of ProgQoS Control for 2-1 Interconnect • Arbitration scheme In the AXI interconnect, you can configure each MI separately to contain an arbitration scheme. This scheme is further classified as: − Non-programmable RR scheme −...
Page 480 S5PC110_UM 1 BUS CONFIGURATION 1.1.1.2 Round-robin (RR) Scheme In the RR scheme, you can select the following design time: • Number of used slots • SI to which these slots are allocated • Order of slots There must be at least one slot per connected SI and up to 32 slots. By allocating multiple slots for a SI, you can allocate access to the slave on average, in proportion to the number of slots.
Page 481 1 BUS CONFIGURATION S5PC110_UM 1.1.1.3 Least Recently Granted Scheme In the Least Recently Granted (LRG) scheme, each connected SI has a single slot associated with it, but each interface also has a priority value. This priority value, whose post-reset value can be configured at design time, programmed, or interrogated through the APB programming interface, can make the arbiter behave as: •...
Page 482: Register Description
1 BUS CONFIGURATION S5PC110_UM 1.2 REGISTER DESCRIPTION 1.2.1 REGISTER MAP Register Address Description Reset Value ASYNC_CONFIG0 0xE0F0_0000 Synchronizer configuration register 0x0000_0001 ASYNC_CONFIG1 0xE1F0_0000 Synchronizer configuration register 0x0000_0001 ASYNC_CONFIG2 0xF180_0000 Synchronizer configuration register 0x0000_0001 ASYNC_CONFIG3 0xF190_0000 Synchronizer configuration register 0x0000_0001 ASYNC_CONFIG4 0xF1A0_0000 Synchronizer configuration register 0x0000_0001...
Page 483: Synchronizer Configuration Register (Async_Config0~10, R/W)
1 BUS CONFIGURATION S5PC110_UM 1.2.2 SYNCHRONIZER CONFIGURATION REGISTER (ASYNC_CONFIG0~10, R/W) ASYNC_CONFIG0~10 Description Initial State Reserved [31:1] Reserved HALF_SYNC_SEL Use half synchronizer for asynchronous clock domain crossing. HALF_SYNC_SEL field of ASYNC_CONFIG0~10 registers decides whether to use half or full synchronization for synchronizer, which separates two different clock domains.
Page 484: Coresight
S5PC110_UM 2 CORESIGHT CORESIGHT 2.1 CORESIGHT SYSTEM OVERVIEW 2.1.1 ABOUT CORESIGHT SYSTEMS GENERALS CoreSight systems provide the entire infrastructure required to debug, monitor, and optimize the performance of a complete System on Chip (SoC) design. There are historically three main ways of debugging an ARM processor based SoC: •...
Page 485: Key Features Of Coresight
S5PC110_UM 2 CORESIGHT 2.1.2 KEY FEATURES OF CORESIGHT 2.1.2.1 Debug Access You gain debug access in CoreSight systems through the Debug Access Port (DAP) that provides: • Real-time access to physical memory without halting the core and without any target resident code •...
Page 486 S5PC110_UM 2 CORESIGHT Figure 2-1 DAP Connections Inside a SoC Cross Triggering The Embedded Cross Trigger (ECT), comprising of the Cross Trigger Interface (CTI) and Cross Trigger Matrix (CTM), provides a standard interconnect mechanism to pass debug or profiling events around the SoC. The ECT provides a standard mechanism to connect different signal types.
Page 487 S5PC110_UM 2 CORESIGHT 2.1.2.3 Coresight System in S5PC110 S5PC110 is single processor system with CortexA8 core. Its main bus system is based on AMBA3 AXI interconnects. It does not support Serial Wire debug port protocol. shows configuration of debugging system.
Page 488 Figure 2-3 Debugger Register Map of S5PC110 2.1.2.4 Authentication for Secure JTAG Operation S5PC110 supports Secure JTAG by using authentication signal of cortexA8 and coresight system. To set the secure JTAG mode can program Secure JTAG key e-fuse bit. •...
Page 489 S5PC110_UM 2 CORESIGHT By writing the passwords in predefined sequence, the authentication can be done. After authentication, the authentication signals are selectively asserted as defined in Table 2-1. Table 2-1 Authentication Signal Rule JTAG JTAG Access Mode DBGEN NIDEN SPIDEN SPNIDEN Detect lock on...
Page 490: Debug Access Port
S5PC110_UM 2 CORESIGHT 2.2 DEBUG ACCESS PORT 2.2.1 ABOUT DEBUG ACCESS PORT The Debug Access Port (DAP) is an implementation of ARM Debug Interface version 5 (ADIv5) comprising a number of components supplied in a single configuration. All the supplied components fit into the various architectural components for Debug Ports (DPs), which are used to access the DAP from an external debugger and Access Ports (APs), to access on-chip system resources.
Page 491 S5PC110_UM 2 CORESIGHT Figure 2-4 Structure of the Coresight DAP Components...
Page 492: Etb
S5PC110_UM 2 CORESIGHT 2.3 ETB 2.3.1 ABOUT THE ETB The ETB provides on-chip storage of trace data using 32-bit RAM. shows the main ETB blocks. The Figure 2-5 ETB accepts trace data from CoreSight trace source components through an AMBA Trace Bus (ATB). The ETB contains the following blocks: •...
Page 493: About The Ect
S5PC110_UM 2 CORESIGHT 2.3.2 ABOUT THE ECT The ECT provides an interface to the debug system as shown in This enables an ARM subsystem to Figure 2-6. interact, that is cross trigger, with each other. The debug system enables debug support for multiple cores, together with cross triggering between the cores and their respective internal embedded trace macrocells.
Page 494: Access Controller (Tzpc)
TZPC provides a software interface to the protection bits in a secure system in a TrustZone design. It provides system flexibility that enables to configure different areas of memory as secure or non-secure. The S5PC110 comprises of four TZPC. 3.1.1 KEY FEATURES OF ACCESS CONTROLLER (TZPC)
Page 495: Functional Description
S5PC110_UM 3 ACCESS CONTROLLER (TZPC) 3.2 FUNCTIONAL DESCRIPTION The TZPC provides a software interface to set up memory areas as secure or non-secure. The two ways to set up memory area as secure or non-secure is as follows: • Programmable protection bits that can be allocated to memory area as determined by the external decoder. •...
Page 496: Tzpc Configuration
S5PC110_UM 3 ACCESS CONTROLLER (TZPC) 3.3 TZPC CONFIGURATION Table 3-1 TZPC Table TZPC0 TZPC1 TZPC2 TZPC3 Register Module Name Module Name Module Name Module Name XBLOCK* CHIPID HDMI_CEC TBLOCK* SYSCON UBLOCK* DMC0 GPIO GBLOCK* DMC1 HDMI_LINK AUDIO(I2S0)** TZPCDECPROT0 MDMA INTC* DSIM IEM_APC I2S2...
Page 497 S5PC110_UM 3 ACCESS CONTROLLER (TZPC) * XBLOCK, TBLOCK, UBLOCK, GBLOCK, LBLOCK, SBLOCK, CBLOCK and INTC Refer to of Section 2-3.S5PC110_CMU. Figure 3-1 ** AUDIO includes I2S0. If non-secure master accesses to secure slave area, DECERR occurs. Table 3-2 TZPC Transfer Attribute Master Attribute Transfer Attribute Slave/Area Attribute...
Page 498: Register Discription
S5PC110_UM 3 ACCESS CONTROLLER (TZPC) 3.4 REGISTER DISCRIPTION 3.4.1 REGISTER MAP Table 3-3 TZPC Registers Register Address Description Reset Value TZPC0 TZPCR0SIZE 0xF150_0000 Specifies the Secure RAM Region Size 0x00000000 Register TZPCDECPROT0Stat 0xF150_0800 Specifies the Decode Protection 0 Status 0x00000000 Register TZPCDECPROT0Set 0xF150_0804...
Page 499 S5PC110_UM 3 ACCESS CONTROLLER (TZPC) Register Address Description Reset Value TZPCR0SIZE 0xFAD0_0000 Not used 0x00000200 TZPCDECPROT0Stat 0xFAD0_0800 Specifies the Decode Protection 0 Status 0x00000000 Register TZPCDECPROT0Set 0xFAD0_0804 Specifies the Decode Protection 0 Set Register TZPCDECPROT0Clr 0xFAD0_0808 Specifies the Decode Protection 0 Clear Register TZPCDECPROT1Stat 0xFAD0_080C...
Page 500 S5PC110_UM 3 ACCESS CONTROLLER (TZPC) Register Address Description Reset Value TZPCDECPROT1Stat 0xE060_080C Specifies the Decode Protection 1 Status 0x00000000 Register TZPCDECPROT1Set 0xE060_0810 Specifies the Decode Protection 1 Set Register TZPCDECPROT1Clr 0xE060_0814 Specifies the Decode Protection 1 Clear Register TZPCDECPROT2Stat 0xE060_0818 Specifies the Decode Protection 2 Status 0x00000000 Register...
Page 501 S5PC110_UM 3 ACCESS CONTROLLER (TZPC) Register Address Description Reset Value TZPCDECPROT2Stat 0xE1C0_0818 Not used 0x00000000 TZPCDECPROT2Set 0xE1C0_081C Not used TZPCDECPROT2Clr 0xE1C0_0820 Not used TZPCDECPROT3Stat 0xE1C0_0824 Not used 0x00000000 TZPCDECPROT3Set 0xE1C0_0828 Not used TZPCDECPROT3Clr 0xE1C0_082C Not used TZPCPERIPHID0 0xE1C0_0FE0 Specifies the TZPC Peripheral Identification 0x00000070 Register 0 TZPCPERIPHID1...
Page 502 S5PC110_UM 3 ACCESS CONTROLLER (TZPC) 3.4.1.1 Secure RAM Region Size Register (TZPCR0SIZE(TZPC0), RW, Address = 0xF150_0000) TZPCR0SIZE Description Initial State Reserved [31:6] Read undefined. Write as zero. R0Size [5:0] Secure RAM region size in 4KB steps. 0x00000000 = no secure region 0x00000001 = 4KB secure region 0x00000002 = 8KB secure region …...
Page 503 S5PC110_UM 3 ACCESS CONTROLLER (TZPC) 3.4.1.3 Decode Protection 0-2 Set Registers • TZPCDECPROTxSet(TZPC0), W, Address = 0xF150_0804, 0xF150_0810, 0xF150_081C • TZPCDECPROTxSet(TZPC1), W, Address = 0xFAD0_0804, 0xFAD0_0810, 0xFAD0_081C • TZPCDECPROTxSet(TZPC2), W, Address = 0xE060_0804, 0xE060_0810, 0xE060_081C • TZPCDECPROTxSet(TZPC3), W, Address = 0xE1C0_0804, 0xE1C0_0810, 0xE1C0_081C TXPCDECPROTxSet Description Initial State...
Page 504 S5PC110_UM 3 ACCESS CONTROLLER (TZPC) 3.4.1.5 TZPC Peripheral Identification Register 0 (TZPCPERIPHID0, R, Address = 0xF150_0FE0, 0xFAD0_0FE0, 0xE060_0FE0, 0xE1C0_0FE0) TZPCPERIPHID0 Description Initial State Reserved [31:8] Read undefined Partnumber0 [7:0] These bits read back as 0x70 0x70 3.4.1.6 TZPC Peripheral Identification Register 1 (TZPCPERIPHID1, R, Address = 0xF150_0FE4, 0xFAD0_0FE4, 0xE060_0FE4, 0xE1C0_0FE4) TZPCPERIPHID1 Description...
Page 505 S5PC110_UM 3 ACCESS CONTROLLER (TZPC) 3.4.1.9 Identification Register 0 (TZPCPCELLID0, R, Address = 0xF150_0FF0, 0xFAD0_0FF0, 0xE060_0FF0, 0xE1C0_0FF0) TZPCPCELLID0 Description Initial State Reserved [31:8] Read undefined TZPCPCELLID0 [7:0] These bits read back as 0x0D 0x0D 3.4.1.10 Identification Register 1 (TZPCPCELLID1, R, Address = 0xF150_0FF4, 0xFAD0_0FF4, 0xE060_0FF4, 0xE1C0_0FF4) TZPCPCELLID1 Description Initial State...
Page 506 Section 4 INTERRUPT...
Page 507 Table of Contents Vectored Interrupt Controller ..............1-1 1.1 Overview of Vectored Interrupt Controller ....................1-1 1.1.1 Key Features of Vectored Interrupt Controller.................. 1-1 1.2 Nterrupt Source............................1-2 1.3 Functional Description ..........................1-6 1.4 Register Description..........................1-7 1.4.1 Register Map ............................ 1-7...
Page 508: Vectored Interrupt Controller
VECTORED INTERRUPT CONTROLLER 1.1 OVERVIEW OF VECTORED INTERRUPT CONTROLLER The interrupt controller in S5PC110 is composed of four Vectored Interrupt Controller (VIC), ARM PrimeCell PL192 and four TrustZone Interrupt Controller (TZIC), SP890. Three TZIC’s and three VIC’s are daisy-chained to support up to 93 interrupt sources. The TZIC provides a software interface to the secure interrupt system in a TrustZone design.
Page 509: Nterrupt Source
S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.2 NTERRUPT SOURCE The S5PC110 supports interrupt sources as shown in the Table below. Module VIC port no INT Request Remark VIC3 Multimedia, Audio, Security, Etc., PENDN1 (TSADC) ADC1 (TSADC) MMC3 VIC2 SDM_FIQ (security)
Page 510 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Module VIC port no INT Request Remark SDM_IRQ (security) Multimedia, PCM2 Audio, IntFeedCtrl_SSS Security, IntHash_SSS Etc., KEYPAD PENDN (TSADC) ADC (TSADC) SPDIF PCM1 PCM0 AC97 I2S1 I2S0 TVENC I2C_HDMI_DDC HDMI Mixer JPEG FIMC2 FIMC1 FIMC0 ROTATOR LCD[2] LCD[1]...
Page 511 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Module VIC port no INT Request Remark Connectivity, Storage HSMMC0 MODEMIF OTG (usb) UHOST (usb) I2C_HDMI_PHY I2C2 AUDIO_SS SPI1 SPI0 I2C0 UART3 UART2 UART1 UART0 IEM_IEC IEM_APC CORTEX4 (nCTIIRQ) CORTEX3 (nDMAEXTERIRQ) CORTEX2 (nDMAIRQ) CORTEX1 (nDMASIRQ) CORTEX0 (nPMUIRQ) VIC0 FIMC3...
Page 512 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Module VIC port no INT Request Remark System Timer TIMER4 TIMER3 TIMER2 TIMER1 TIMER0 PDMA1 PDMA0 MDMA EINT 16_31 EXT_INT[16] ~ [31] EINT15 EXT_INT[15] EINT14 EXT_INT[14] EINT13 EXT_INT[13] EINT12 EXT_INT[12] EINT11 EXT_INT[11] EINT10 EXT_INT[10] EINT9 EXT_INT[9] EINT8 EXT_INT[8]...
Page 513: Functional Description
S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.3 FUNCTIONAL DESCRIPTION When user clears interrupt pending, user must write 0 to all the VICADDRESS registers (VIC0ADDRESS, VIC1ADDRESS, VIC2ADDRESS, and VIC3ADDRESS).
Page 514: Register Description
S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4 REGISTER DESCRIPTION 1.4.1 REGISTER MAP Register Address Description Reset Value VIC0IRQSTATUS 0xF200_0000 Specifies the IRQ Status Register 0x00000000 VIC0FIQSTATUS 0xF200_0004 Specifies the FIQ Status Register 0x00000000 VIC0RAWINTR 0xF200_0008 Specifies the Raw Interrupt Status Register VIC0INTSELECT 0xF200_000C Specifies the Interrupt Select Register...
Page 515 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC0VECTADDR19 0xF200_014C Specifies the Vector Address 19 Register 0x00000000 VIC0VECTADDR20 0xF200_0150 Specifies the Vector Address 20 Register 0x00000000 VIC0VECTADDR21 0xF200_0154 Specifies the Vector Address 21 Register 0x00000000 VIC0VECTADDR22 0xF200_0158 Specifies the Vector Address 22 Register 0x00000000 VIC0VECTADDR23 0xF200_015C...
Page 516 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC0VECTPRIORITY23 0xF200_025C Specifies the Vector Priority 23 Register VIC0VECTPRIORITY24 0xF200_0260 Specifies the Vector Priority 24 Register VIC0VECTPRIORITY25 0xF200_0264 Specifies the Vector Priority 25 Register VIC0VECTPRIORITY26 0xF200_0268 Specifies the Vector Priority 26 Register VIC0VECTPRIORITY27 0xF200_026C Specifies the Vector Priority 27 Register...
Page 517 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC1PRIORITYDAISY 0xF210_0028 Specifies the Vector Priority Register for Daisy Chain VIC1VECTADDR0 0xF210_0100 Specifies the Vector Address 0 Register 0x00000000 VIC1VECTADDR1 0xF210_0104 Specifies the Vector Address 1 Register 0x00000000 VIC1VECTADDR2 0xF210_0108 Specifies the Vector Address 2 Register 0x00000000 VIC1VECTADDR3...
Page 518 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC1VECTPRIORITY2 0xF210_0208 Specifies the Vector Priority 2 Register VIC1VECTPRIORITY3 0xF210_020C Specifies the Vector Priority 3 Register VIC1VECTPRIORITY4 0xF210_0210 Specifies the Vector Priority 4 Register VIC1VECTPRIORITY5 0xF210_0214 Specifies the Vector Priority 5 Register VIC1VECTPRIORITY6 0xF210_0218 Specifies the Vector Priority 6 Register...
Page 519 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC1PERIPHID3 0xF210_0FEC Specifies the Peripheral Identification 0x00 Register bit 31:24 VIC1PCELLID0 0xF210_0FF0 Specifies the PrimeCell Identification 0x0D Register bit 7:0 VIC1PCELLID1 0xF210_0FF4 Specifies the PrimeCell Identification 0xF0 Register bit 15:9 VIC1PCELLID2 0xF210_0FF8 Specifies the PrimeCell Identification...
Page 520 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC2VECTADDR13 0xF220_0134 Specifies the Vector Address 13 Register 0x00000000 VIC2VECTADDR14 0xF220_0138 Specifies the Vector Address 14 Register 0x00000000 VIC2VECTADDR15 0xF220_013C Specifies the Vector Address 15 Register 0x00000000 VIC2VECTADDR16 0xF220_0140 Specifies the Vector Address 16 Register 0x00000000 VIC2VECTADDR17 0xF220_0144...
Page 521 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC2VECTPRIORITY17 0xF220_0244 Specifies the Vector Priority 17 Register VIC2VECTPRIORITY18 0xF220_0248 Specifies the Vector Priority 18 Register VIC2VECTPRIORITY19 0xF220_024C Specifies the Vector Priority 19 Register VIC2VECTPRIORITY20 0xF220_0250 Specifies the Vector Priority 20 Register VIC2VECTPRIORITY21 0xF220_0254 Specifies the Vector Priority 21 Register...
Page 522 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value Register VIC3SOFTINT 0xF230_0018 Specifies the Software Interrupt Register 0x00000000 VIC3SOFTINTCLEAR 0xF230_001C Specifies the Software Interrupt Clear Register VIC3PROTECTION 0xF230_0020 Specifies the Protection Enable Register VIC3SWPRIORITYMASK 0xF230_0024 Specifies the Software Priority Mask 0xFFFF Register VIC3PRIORITYDAISY...
Page 523 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC3VECTADDR28 0xF230_0170 Specifies the Vector Address 28 Register 0x00000000 VIC3VECTADDR29 0xF230_0174 Specifies the Vector Address 29 Register 0x00000000 VIC3VECTADDR30 0xF230_0178 Specifies the Vector Address 30 Register 0x00000000 VIC3VECTADDR31 0xF230_017C Specifies the Vector Address 31 Register 0x00000000 VIC3VECPRIORITY0 0xF230_0200...
Page 524 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC3ADDRESS 0xF230_0F00 Specifies the Vector Address Register 0x00000000 VIC3PERIPHID0 0xF230_0FE0 Specifies the Peripheral Identification 0x92 Register bit 7:0 VIC3PERIPHID1 0xF230_0FE4 Specifies the Peripheral Identification 0x11 Register bit 15:9 VIC3PERIPHID2 0xF230_0FE8 Specifies the Peripheral Identification 0x04 Register bit 23:16...
Page 525 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value TZIC1IntSelect 0xF290_0008 Specifies the Interrupt Select Register 0x00000000 TZIC1FIQEnable 0xF290_000C Specifies the FIQ Enable Register 0x00000000 TZIC1FIQENClear 0xF290_0010 Specifies the FIQ Enable Clear Register TZIC1FIQBypass 0xF290_0014 Specifies the FIQ Bypass Register 0x00000000 TZIC1Protection 0xF290_0018...
Page 526 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value Register TZIC3IntSelect 0xF2B0_0008 Specifies the Interrupt Select Register 0x00000000 TZIC3FIQEnable 0xF2B0_000C Specifies the FIQ Enable Register 0x00000000 TZIC3FIQENClear 0xF2B0_0010 Specifies the FIQ Enable Clear Register TZIC3FIQBypass 0xF2B0_0014 Specifies the FIQ Bypass Register 0x00000000 TZIC3Protection 0xF2B0_0018...
Page 527 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.1 IRQ Status Register (VICIRQSTATUS, R, Address=0xF200_0000, 0xF210_0000, 0xF220_0000, 0XF230_0000) VICIRQSTATUS Description Initial State IRQStatus [31:0] Shows the status of the interrupts after masking by the 0x00000000 VICINTENABLE and VICINTSELECT Registers: 0 = Interrupt is inactive 1 = Interrupt is active.
Page 528 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.5 Interrupt Enable Register (VICINTENABLE, R/W, Address=0xF200_0010, 0xF210_0010, 0xF220_0010, 0xF230_0010) VICINTENABLE Description Initial State IntEnable [31:0] Enables the interrupt request lines, which allows the interrupts to 0x00000000 reach the processor. Read: 0 = Disables Interrupt 1 = Enables Interrupt Use this register to enable interrupt.
Page 529 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.8 Software Interrupt Clear Register (VICSOFTINTCLEAR, W, Address=0xF200_001C, 0xF210_001C, 0xF220_001C, 0xF230_001C) VICSOFTINTCLEAR Description Initial State SoftIntClear [31:0] Clears corresponding bits in the VICSOFTINT Register: 0 = No effect 1 = Disables Software interrupt in the VICSOFTINT Register. There is one bit of the register for each interrupt source.
Page 530 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.11 Software Priority Mask Register (VICSWPRIORITYMASK, R/W, Address=0xF200_0024, 0xF210_0024, 0xF220_0024, 0xF230_0024) VICSWPRIORITYMASK Description Initial State Reserved [31:16] Reserved, read as 0, do not modify SWPriorityMask [15:0] Controls software masking of the 16 interrupt priority levels: 0xFFFF 0 = Interrupt priority level is masked 1 = Interrupt priority level is not masked...
Page 531 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.15 VICPERIPHID1 Register (VICPERIPHID1, R, Address=0xF200_0FE4, 0xF210_0FE4, 0xF220_0FE4, 0xF230_0FE4) VICPERIPHID1 Description Initial State [31:8] Reserved, read as 0, do not modify. Designer0 [7:4] These bits read back as 0x1. Partnumber1 [3:0] These bits read back as 0x1. 1.4.1.16 VICPERIPHID2 Register (VICPERIPHID2, R, Address=0xF200_0FE8, 0xF210_0FE8, 0xF220_0FE8, 0xF230_0FE8) VICPERIPHID2...
Page 532 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.19 VICPCELLID1 Register (VICPCELLID1, R, Address=0xF200_0FF4, 0xF210_0FF4, 0xF220_0FF4, 0xF230_0FF4) VICPCELLID1 Description Initial State [31:8] Reserved, read as 0, do not modify. VICPCellID1 [7:0] These bits read back as 0xF0. 0xF0 1.4.1.20 VICPCELLID2 Register (VICPCELLID2, R, Address=0xF200_0FF8, 0xF210_0FF8, 0xF220_0FF8, 0xF230_0FF8) VICPCELLID2 Description...
Page 533 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.24 Interrupt select register (TZICIntSelect, R/W, Address=0xF280_0008, 0xF290_0008, 0xF2A0_0008, 0xF2B0_0008) TZICRawIntr Description Initial State IntSelect [31:0] Selects whether the interrupt source generates an FIQ 0x00000000 interrupt or passes straight through to TZICIRQOUT. 0 = Interrupt passes through to TZICIRQOUT 1 = Interrupt is available for FIQ generation 1.4.1.25 FIQ Enable Register (TZICFIQEnable, R/W, Address=0xF280_000C, 0xF290_000C, 0xF2A0_000C, 0xF2B0_000C)
Page 534 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.28 Protection Register (TZICProtection, R/W, Address=0xF280_0018, 0xF290_0018, 0xF2A0_0018, 0xF2B0_0018) TZICProtection Description Initial State [31:1] Read undefined. Write as 0. Protection Enables or disables protected register access: 0 = Disables Protection mode 1 = Enables Protection mode. If enabled, you can only make privileged mode access (reads and writes) to the TZIC.
Page 535 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.32 Peripheral Identification Register (TZICPeriphID1, R, Address=0xF280_0FE4, 0xF290_0FE4, 0xF2A0_0FE4, 0xF2B0_0FE4) TZICPeriphID1 Description Initial State [31:8] Read undefined Designer0 [7:4] These bits read back as 0x1 Partnumber1 [3:0] These bits read back as 0x8 1.4.1.33 Peripheral Identification Register (TZICPeriphID2, R, Address=0xF280_0FE8, 0xF290_0FE8, 0xF2A0_0FE8, 0xF2B0_0FE8) TZICPeriphlD2 Description...
Page 536 S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.37 Identification Register (TZICPCellID2, R, Address=0xF280_0FF8, 0xF290_0FF8, 0xF2A0_0FF8, 0xF2B0_0FF8) TZICPCellID2 Description Initial State [31:8] Read undefined TZICPCellID2 [7:0] These bits read back as 0x05 0x05 1.4.1.38 Identification Register (TZICPCellID3 Register, R, Address=0xF280_0FFC, 0xF290_0FFC, 0xF2A0_0FFC, 0xF2B0_0FFC) TZICPCellID3 Description Initial State...
Page 537 Section 5 MEMORY...
Page 538 Table of Contents DRAM Controller ..................1-1 1.1 Overview of DRAM Controller........................1-1 1.1.1 Introduction of DRAM Controller....................... 1-1 1.1.2 Key Features of DRAM Controller ....................1-1 1.1.3 Supports Clock frequency up to 200MHz Block Diagram ..............1-2 1.2 Functional Description ..........................1-3 1.2.1 Initialization ............................
Page 539 External Bus Interface ................6-1 6.1 Overview of External bus Interface ......................6-1 6.2 Key Features of S5PC110 EBI ........................ 6-1 6.3 Block Diagram of Memory Interface through EBI ..................6-2 6.4 Clock Scheme of Memory Controllers and EBI ..................6-3...
Page 541 List of Figures Figure Title Page Number Number Figure 1-1 Overall Block Diagram ........................1-2 Figure 1-2 Linear Address Mapping........................1-7 Figure 1-3 Interleaved Address Mapping ......................1-8 Figure 1-4 Timing Diagram of Timeout Precharge................... 1-10 Figure 1-5 Adaptive DRAM QoS Scheme Configuration ................. 1-12 Figure 1-6 Timing Diagram of Read Data Capture (DDR2, zero delay, RL=3, rd_fetch=1) ......
Page 542 Figure 5-1 Block Diagram of Compact Flash Controller ..................5-2 Figure 5-2 PIO Mode Waveform ........................5-4 Figure 5-3 Flowchart for Read / Write in PIO Class................... 5-6 Figure 5-4 MDMA Timing Diagram ........................5-7 Figure 5-5 UDMA- In Operation (Terminated by Device)................... 5-9 Figure 5-6 UDMA - In Operation (Terminated by Host) ...................
Page 543 Number Number Table 1-1 Fast Qos index table ........................1-13 Table 1-2 Master Transaction ID for DMC0 in S5PC110................. 1-48 Table 1-3 Master Transaction ID for DMC1 in S5PC110................. 1-49 Table 3-1 OneNAND Controller Memory Map ....................3-6 Table 3-2 OneNAND Chip #0 (nCE[0]) Address Map (If the OneNAND device is Connected to nCE[0])..
Page 544: Dram Controller
To support high-speed memory devices, the DRAM controller uses a SEC DDR PHY interface. The controller includes an advanced embedded scheduler to utilize memory device efficiently and an optimized pipeline stage to minimize latency. S5PC110 has two independent DRAM Controllers and Ports, namely, DMC0 and DMC1. 1.1.2 KEY FEATURES OF DRAM CONTROLLER •...
Page 545: Supports Clock Frequency Up To 200Mhz Block Diagram
S5PC110_UM 1 DRAM CONTROLLER 1.1.3 SUPPORTS CLOCK FREQUENCY UP TO 200MHZ BLOCK DIAGRAM Figure 1-1 Overall Block Diagram shows the overall block diagram of the controller. The block diagram shows the bus interface block, Figure 1-1 scheduler block, and memory interface block, which connects and interfaces with the SEC LPDDR2 PHY. The bus interface block saves the bus transactions for memory access that come from the AXI slave port to the command queue.
Page 546: Functional Description
S5PC110_UM 1 DRAM CONTROLLER 1.2 FUNCTIONAL DESCRIPTION 1.2.1 INITIALIZATION An Initialization procedure consists of PHY DLL initialization, setting controller register and memory initialization. For memory initialization, refer to JEDEC specifications and data sheets of memory devices. There are three different memory types, namely, LPDDR, LPDDR2, and DDR2. According to the memory types, initialization sequences are as follows.
Page 547 S5PC110_UM 1 DRAM CONTROLLER 17. Issue an EMRS command using the DirectCmd register to program the operating parameters. 18. If there are two external memory chips, perform steps 14~17 for chip1 memory device. 19. Set the ConControl to turn on an auto refresh counter. 20.
Page 548 S5PC110_UM 1 DRAM CONTROLLER 17. Issue a MRS command using the DirectCmd register to reset memory device and program the operating parameters. 18. Wait for minimum 1us. 19. Issue a MRR command using the DirectCmd register to poll the DAI bit of the MRStatus register to know whether Device Auto-Initialization is completed or not.
Page 549: Address Mapping
S5PC110_UM 1 DRAM CONTROLLER 15. Wait for minimum 400ns. 16. Issue a PALL command using the DirectCmd register. 17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters. 18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters. 19.
Page 550 S5PC110_UM 1 DRAM CONTROLLER 1.2.2.1 Linear Mapping Figure 1-2 Linear Address Mapping As shown in 1-2, the linear mapping method maps the AXI address in the order of bank, row, column and Figure width. Since the bank address does not change for at least one bank size, applications that use linear address mapping have a high possibility to access the same bank.
Page 551: Low Power Operation
S5PC110_UM 1 DRAM CONTROLLER 1.2.2.2 Interleaved Mapping AXI base address bank0.row0 row density bank1.row0 bank2.row0 bank3.row0 bank0.row1 AXI offset address bank1.row1 bank2.row1 bank3.row1 bank column width bank0.rown bank1.rown bank2.rown Interleaved mapping : AXI offset address = {row, bank, column, width} bank3.rown Figure 1-3 Interleaved Address Mapping...
Page 552: Precharge Policy
S5PC110_UM 1 DRAM CONTROLLER 1.2.3.2 Dynamic Power Down The SDRAM device has an active/ precharge power down mode. This mode is entered if CKE becomes LOW. To enter active power down mode minimum one row of a bank must be open. To enter precharge power down mode CKE must be low.
Page 553 S5PC110_UM 1 DRAM CONTROLLER 1.2.4.1 Bank Selective Precharge Policy Since applications include different page policy preferences, it is hard for the engineer to decide whether to use open page policy, or close page (auto precharge) policy. Instead of applying the page policy to entire banks, the bank selective precharge policy allows the user to choose a precharge policy for each bank (Refer to PrechConfig.chip1_policy).
Page 554: Quality Of Service
S5PC110_UM 1 DRAM CONTROLLER 1.2.5 QUALITY OF SERVICE The Quality of Service (QoS) is defined for the controller to increase the arbitration priority of a master that requires low latency read data. The QoS is determined if the control queue (Refer to Figure 1-1Figure 1-1) receives the command through the AXI bus and the QoS count starts depreciating at this moment.
Page 555 S5PC110_UM 1 DRAM CONTROLLER 1.2.5.2 qos_cnt_f To service latency sensitive commands faster, an adaptive DRAM QoS scheme called QoS fast can be enabled. This policy cannot be done by the memory controller itself, but the IP has to observe its FIFO level. For read transactions, for example, when the IP’s FIFO is less than 1/4th full, there is no margin of time available between the FIFO and the memory controller.
Page 556 S5PC110_UM 1 DRAM CONTROLLER If qos fast (Concontrol.qos_fast_en) is enabled, and the master that sent the command has raised the qos_fast flag of it’s specific channel index, instead of qos_cnt (QoSControl(index).qos_cnt) being applied to the command, the QoS Cycles for fast request (QoSControl(index).qos_cnt_f) is applied.
Page 557: Read Data Capture
S5PC110_UM 1 DRAM CONTROLLER 1.2.6 READ DATA CAPTURE A memory device that receives a read command sends the data to the controller after a read latency (i.e. CAS latency). After clearing the DQS, the PHY uses the PHY DLL to phase shift the DQS 90 degrees. Using the shifted DQS, the PHY samples the read data and saves the data into the read data input FIFO, which is located inside the PHY.
Page 558 S5PC110_UM 1 DRAM CONTROLLER is for DDR2 having an internal DLL. An internal DLL exists which allows it to send the data after an Figure 1-6 exact amount of read latency. If we assume there are minimal or no board/ PHY input delay, if sampling the negedge (Q1, Q3 sampling), since the data gets saved into the PHY read data input FIFO, the controller sends the read data to the AXI read channel in ‘read latency + 1(read fetch)’...
Page 559 S5PC110_UM 1 DRAM CONTROLLER To calculate the DDR2 rd_fetch value: rd_fetch DDR2) = INT((Delay + 0.5T + 0.25T)/T) = INT(Delay/T + 0.75), Delay: board delay + PHY input/output delay, T: clock period, INT(x): the rounded-up integer value of x Therefore, rd_fetch must have minimum one value. Figure 1-8 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, zero delay, RL=3, rd_fetch=1)
Page 560 S5PC110_UM 1 DRAM CONTROLLER Figure 1-9 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, non-zero delay, RL=3, rd_fetch=2) If a delay exists as shown in 1-9, a bigger value should be assigned to rd_fetch Figure 1-17...
Page 561 S5PC110_UM 1 DRAM CONTROLLER Figure 1-10 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, low frequency, RL=3, rd_fetch=0) tDQSCK + Delay is relatively small compared to the clock period during low frequencies as shown in Figure 1-10. In this situation, negedge sampling happens before read latency and therefore read fetch is set to zero. To calculate the LPDDR/LPDDR2 rd_fetch value: rd_fetch (LPDDR/LPDDR2) = INT((-1 + Delay + 0.5T + 0.25T)/T) = INT(Delay/T - 0.25), Delay: board delay + PHY input delay, T: clock period, INT(x): the rounded-up integer value of x...
Page 562: I/O Description
S5PC110_UM 1 DRAM CONTROLLER 1.3 I/O DESCRIPTION Signal Description Type DDR2SEL Memory Type Selection XDDR2SEL dedicated (0: LPDDR1, 1: DDR2, LPDDR2) SCLK Memory Clock Xm1SCLK dedicated nSCLK Memory Negative Clock Xm1nSCLK dedicated RASn Row Address Selection Xm1RASn dedicated CASn Column Address Selection Xm1CASn dedicated Write Enable...
Page 563: Pad Mux For Address Configuration
S5PC110_UM 1 DRAM CONTROLLER 1.3.1 PAD MUX FOR ADDRESS CONFIGURATION PAD Name Config. 1 Config. 2 Config. 3 Config. 4 LPDDR2 Xm1ADDR[0] ADDR_0 ADDR_0 ADDR_0 ADDR_0 CA_0 Xm1ADDR[1] ADDR_1 ADDR_1 ADDR_1 ADDR_1 CA_1 Xm1ADDR[2] ADDR_2 ADDR_2 ADDR_2 ADDR_2 CA_2 Xm1ADDR[3] ADDR_3 ADDR_3 ADDR_3...
Page 564: Register Description
S5PC110_UM 1 DRAM CONTROLLER 1.4 REGISTER DESCRIPTION 1.4.1 REGISTER MAP Register Address Description Reset Value DMC0 CONCONTROL 0xF000_0000 R/W Specifies the Controller Control Register 0x0FFF_1350 MEMCONTROL 0xF000_0004 R/W Specifies the Memory Control Register 0x0020_2100 MEMCONFIG0 0xF000_0008 R/W Specifies the Memory Chip0 Configuration Register 0x20F0_0312 MEMCONFIG1 0xF000_000C...
Page 565 S5PC110_UM 1 DRAM CONTROLLER Register Address Description Reset Value QOSCONFIG2 0xF000_0074 R/W Specifies the Quality of Service Configuration 0x0000_0000 Register 2 QOSCONTROL3 0xF000_0078 R/W Specifies the Quality of Service Control Register 3 0x0000_0000 QOSCONFIG3 0xF000_007C R/W Specifies the Quality of Service Configuration 0x0000_0000 Register 3 QOSCONTROL4...
Page 566 S5PC110_UM 1 DRAM CONTROLLER Register Address Description Reset Value QOSCONFIG15 0xF000_00DC R/W Specifies the Quality of Service Configuration 0x0000_0000 Register 15 DMC1 CONCONTROL 0xF140_0000 R/W Specifies the Controller Control Register 0x0FFF1350 MEMCONTROL 0xF140_0004 R/W Specifies the Memory Control Register 0x00202100 MEMCONFIG0 0xF140_0008 R/W Specifies the Memory Chip0 Configuration Register...
Page 567 S5PC110_UM 1 DRAM CONTROLLER Register Address Description Reset Value QOSCONTROL3 0xF140_0078 R/W Specifies the Quality of Service Control Register 3 0x00000000 QOSCONFIG3 0xF140_007C R/W Specifies the Quality of Service Configuration 0x00000000 Register 3 QOSCONTROL4 0xF140_0080 R/W Specifies the Quality of Service Control Register 4 0x00000000 QOSCONFIG4 0xF140_0084...
Page 568 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.1 Controller Control Register (ConControl, R/W, Address = 0xF000_0000, 0xF140_0000) Initial CONCONTROL Description State Reserved [31:28] Should be zero timeout_cnt [27:16] Default Timeout Cycles 0xFFF 0xn = n aclk cycles (aclk: AXI clock) This counter prevents transactions in command queue from starvation.
Page 569 S5PC110_UM 1 DRAM CONTROLLER Initial CONCONTROL Description State drv_en PHY Driving 0x0 = Disables 0x1 = Enables During the high-Z state of the memory bidirectional pins, PHY drives these pins with the zeros or pull down these pins for preventing current leakage. Set PhyControl1.drv_type register to select driving type.
Page 570 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.2 Memory Control Register (MemControl, R/W, Address = 0xF000_0004, 0xF140_0004) Initial MEMCONTROL Description State Reserved [31:23] Should be zero [22:20] Memory Burst Length 0x0 = Reserved 0x1 = 2 0x2 = 4 0x3 = 8 0x4 = 16 0x5 ~ 0x7 = Reserved In case of DDR2/ LPDDR2, the controller only supports burst length 4.
Page 571 S5PC110_UM 1 DRAM CONTROLLER Initial MEMCONTROL Description State mclk cycles to wait until timeout precharge precharges the open bank. Refer to “1.2.4.2 . Timeout Precharge”. dpwrdn_type [3:2] Type of Dynamic Power Down 0x0 = Active/ Precharge power down 0x1 = Force precharge power down 0x2 ~ 0x3 = Reserved Refer to “1.2.3.2 Dynamic Power...
Page 572 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.3 Memory Chip0 Configuration Register (MemConfig0, R/W, Address=0xF000_0008, 0xF140_0008) Initial MEMCONFIG0 Description State chip_base [31:24] AXI Base Address DMC0: 0x20 AXI base address [31:24] = chip_base DMC1: For example, if chip_base = 0x20, then AXI base address of 0X40 memory chip0 becomes 0x2000_0000.
Page 573 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.4 Memory Chip1 Configuration Register (MemConfig1, R/W, Address = 0xF000_000C, 0xF140_000C) Initial MEMCONFIG1 Description State chip_base [31:24] AXI Base Address DMC0: 0x30 AXI base address [31:24] = chip_base, DMC1: For example, if chip_base = 0x28, then AXI base address of 0x60 chip1 becomes 0x2800_0000.
Page 574 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.5 Memory Direct Command Register (DirectCmd, R/W, Address = 0xF000_0010, 0xF140_0010) Initial DIRECTCMD Description State Reserved [31:28] Should be zero. cmd_type [27:24] Type of Direct Command 0x0 = MRS/EMRS (mode register setting), 0x1 = PALL (all banks precharge), 0x2 = PRE (per bank precharge), 0x3 = DPD (deep power down), 0x4 = REFS (self refresh),...
Page 575 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.6 Precharge Policy Configuration Register (PrechConfig, R/W, Address = 0xF000_0014, 0xF140_0014) Initial PRECHCONFIG Description State tp_cnt [31:24] Timeout Precharge Cycles 0xFF 0xn = n mclk cycles, If the timeout precharge function (MemControl.tp_en) is enabled and the timeout precharge counter becomes zero, the controller forces the activated memory bank into the precharged state.
Page 576 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.7 PHY Control0 Register (PhyControl0, R/W, Address = 0xF000_0018, 0xF140_0018) Initial PHYCONTROL0 Description State ctrl_force [31:24] DLL Force Delay This field is used instead of ctrl_lock_value[9:2] from the PHY DLL when ctrl_dll_on is LOW. (i.e. If the DLL is off, this field is used to generate 270' clock and shift DQS by 90'.) ctrl_inc [23:16] DLL Delay Increment...
Page 577 S5PC110_UM 1 DRAM CONTROLLER Power up & Memory DLL Lock Memory Acess PLL lock Initialization rst_n W rite c trl _s ta rt_p o in t v al ue ctrl_start_point Wri te ctr l_ in c va lu e ctrl_inc D L L Lo ck St art ctrl_start D LL L oc ke d...
Page 578 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.8 PHY Control1 Register (PhyControl1, R/W, Address = 0xF000_001C, 0xF140_001C) Initial PHYCONTROL1 Description State Reserved [31:23] Should be zero ctrl_offsetd [22:16] This field is for debug purpose. If this field is fixed, field value must not be changed during operation.
Page 579 S5PC110_UM 1 DRAM CONTROLLER Use DQS cleaning to remove high-Z state of DQS. M e m o r y P H Y A D C T / C M D C K / C K io _ ck _o u t G A T E O io _g a t e _ ou t t D L...
Page 580 S5PC110_UM 1 DRAM CONTROLLER Delay line programming value; tDL ≈ t AC + 2*(tB+tC+tD). tDL = tF (ctrl_shiftc[2:0]) + tV (ctrl_offsetc[6:0]) If ctrl_shiftc[2:0] is 3'b100, tF is Tperiod/8 ≈ 0.9375ns. (If tCK is 7.5ns) If ctrl_offsetc[6:0] is 7'b00010_00, tV is 0.320ns(40ps * 8) @ worst case (if tFS = 40ps) Therefore tDL = tF + tV = 0.9375ns + 0.320ns = 1.2575ns Figure 1-13 DQS Cleaning for LPDDR if tAC Min Figure 1-14 DQS Cleaning for LPDDR if tAC Max...
Page 581 S5PC110_UM 1 DRAM CONTROLLER Figure 1-15 DQS cleaning for DDR2 1.4.1.9 Dynamic Power Down Configuration Register (PwrdnConfig, R/W, Address = 0xF000_0028, 0xF140_0028) Initial PWRDNCONFIG Description State dsref_cyc [31:16] Number of Cycles for Dynamic Self Refresh Entry 0xFFFF 0xn = n aclk cycles, If the command queue is empty for n+1 cycles, the controller forces the memory device into self refresh state.
Page 582 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.10 AC Timing Register for Auto Refresh of memory (TimingAref, R/W, Address = 0xF000_0030, 0xF140_0030) Initial TIMINGAREF Description State Reserved [31:16] Should be zero t_refi [15:0] Average Periodic Refresh Interval 0x40E Should be minimum memory tREFI (all bank) < t_refi * T(mclk), For example, for the all bank refresh period of 7.8us, and an mclk frequency of 133MHz, the following value should be programmed :...
Page 583 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.12 AC Timing Register for the Data of memory (TimingData, R/W, Address = 0xF000_0038, 0xF140_0038) Initial TIMINGDATA Description State t_wtr [31:28] Internal write to Read command delay, in cycles t_wtr * T(mclk) should be greater than or equal to the minimum value of memory tWTR.
Page 584 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.13 AC Timing Register for the Power mode of Memory (TimingPower, R/W, Address = 0xF000_003C, 0xF140_003C) Initial TIMINGPOWER Description State Reserved [31:30] Should be zero t_faw [29:24] Four Active Window t_faw * T(mclk) should be greater than or equal to the minimum value of memory tFAW t_xsr [23:16]...
Page 585 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.14 PHY Status Register (PhyStatus, Read Only, Address=0xF000_0040, 0xF140_0040) Initial PHYSTATUS0 Description State Reserved [31:14] Should be zero ctrl_lock_value [13:4] Locked Delay Locked delay line encoding value ctrl_lock_value[9:2]: number of delay cells for coarse lock ctrl_lock_value[1:0]: control value for fine lock Reserved Should be zero ctrl_locked...
Page 586 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.15 Memory Chip0 Status Register (Chip0Status, Read Only, Address = 0xF000_0048, 0xF140_0048) Initial CHIP0STATUS Description State bank7_state [31:28] The current state of bank 7 of memory chip0 bank6_state [27:24] The current state of bank 6 of memory chip0 bank5_state [23:20] The current state of bank 5 of memory chip0...
Page 587 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.16 Memory Chip1 Status Register (Chip1Status, Read Only, Address=0xF000_004C, 0xF140_004C) Initial CHIP1STATUS Description State bank7_state [31:28] The current state of bank 7 of SDRAM chip1 bank6_state [27:24] The current state of bank 6 of SDRAM chip1 bank5_state [23:20] The current state of bank 5 of SDRAM chip1...
Page 588 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.17 Counter Status Register for the Auto Refresh (ArefStatus, R, Address=0xF000_0050, 0xF140_0050) Initial AREFSTATUS Description State Reserved [31:16] Should be zero aref_cnt [15:0] Current Value of Auto Refresh Counter 0xFFFF Shows the current value of all bank auto refresh counter. This is updated if a new t_refi is programmed into the TimingAref register and decreases by 1 at the rising edge of mclk.
Page 589 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.20 PHY Test Register 1 (PhyTest1, R, Address = 0xF000_005C, 0xF140_005C) Initial PHYTEST1 Description State ctrl_fb_cnt3 [31:24] Count value for data3 channel ctrl_fb_cnt2 [23:16] Count value for data2 channel ctrl_fb_cnt1 [15:8] Count value for data1 channels ctrl_fb_cnt0 [7:0] Count value for data0 channel...
Page 590 S5PC110_UM 1 DRAM CONTROLLER 1.4.1.22 Quality of Service Configuration Register n (QosConfig n, R/W, Address = 0xF000_0064 + 8n (n=0~15, integer), 0xF140_0064 + 8n (n=0~15, integer) Initial QOSCONFIGn Description State qos_mask [31:16] QoS Mask Bits This is used to mask the incoming ARID/AWID to compare with the qos_id.
Page 591 S5PC110_UM 1 DRAM CONTROLLER Table 1-2 Master Transaction ID for DMC0 in S5PC110 Transaction Transaction ID Description Master 14’b000_0000_0xxx_x000 14’b000_000x_xxx0_0001 14’b000_000x_xxx1_0001 FIMC0 14’b00x_xxx0_0000_0010 FIMC1 14’b00x_xxx0_0100_0010 FIMC2 14’b00x_xxx0_1000_0010 JPEG 14’b000_0000_1100_0010 14’b000_0001_0000_0010 FIMD_W0 14’b000_0000_0001_0010 FIMD window 0 FIMD_W4 14’b000_0001_0001_0010 FIMD window 4 FIMD_W1 14’b000_0000_0101_0010...
Page 592 S5PC110_UM 1 DRAM CONTROLLER Table 1-3 Master Transaction ID for DMC1 in S5PC110 Transaction Transaction ID Description Master 14’b000_0000_0xxx_x000 14’b000_000x_xxx0_1100 14’b000_000x_xxx1_0100 FIMC0 14’b00x_xxx0_0000_1011 FIMC1 14’b00x_xxx0_0100_1011 FIMC2 14’b00x_xxx0_1000_1011 JPEG 14’b000_0000_1100_1011 14’b000_0001_0000_1011 FIMD_W0 14’b000_0000_0001_1011 FIMD window 0 FIMD_W4 14’b000_0001_0001_1011 FIMD window 4 FIMD_W1 14’b000_0000_0101_1011 FIMD window 1...
Page 593: Srom Controller
2.1 SROM CONTROLLER 2.1.1 OVERVIEW OF SROM CONTROLLER S5PC110 SROM Controller (SROMC) support external 8 / 16-bit NOR Flash/ PROM/ SRAM memory. S5PC110 SROM Controller supports 6-bank memory up to maximum 16Mbyte per bank. 2.1.2 KEY FEATURES OF SROM CONTROLLER •...
Page 594: Functional Description
S5PC110_UM 2 SROM CONTROLLER 2.2 FUNCTIONAL DESCRIPTION SROM Controller supports SROM interface for Bank0 to Bank5. 2.2.1 NWAIT PIN OPERATION If the WAIT signal corresponding to each memory bank is enabled, the external nWAIT pin should prolong the duration of nOE while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the next clock after sampling nWAIT is high.
Page 595: Programmable Access Cycle
S5PC110_UM 2 SROM CONTROLLER 2.2.2 PROGRAMMABLE ACCESS CYCLE HCLK ADDR ADDRESS 0 ADDRESS 1 Tcah Tacs nGCS Tcoh Tcos Tacc Tacp DATA(R) DATA 0 DATA 1 Tacs = 2-cycle Tacp = 2-cycle Tcos = 2-cycle Tcoh = 2-cycle Tacc = 3-cycle Tcah = 2-cycle Figure 2-3 SROM Controller Read Timing Diagram...
Page 596: I/O Description
S5PC110_UM 2 SROM CONTROLLER 2.3 I/O DESCRIPTION Signal Description Type nGCS[5:0] Output Bank selection signal Xm0CSn[5:0] muxed ADDR[22:0] Output SROM Address bus Xm0ADDR[22:0] muxed Output SROM Output Enable Xm0OEn muxed Output SROM Write Enable Xm0WEn muxed nWBE/nBE [1:0] Output SROM Byte write Enable / Byte Enable Xm0BEn muxed DATA[15:0]...
Page 597: Register Description
S5PC110_UM 2 SROM CONTROLLER 2.4 REGISTER DESCRIPTION 2.4.1 REGISTER MAP Register Address Description Reset Value SROM_BW 0xE800_0000 Specifies the SROM Bus width & wait control 0x0000_0009 SROM_BC0 0xE800_0004 Specifies the SROM Bank0 control register 0x000F_0000 SROM_BC1 0xE800_0008 Specifies the SROM Bank1 control register 0x000F_0000 SROM_BC2 0xE800_000C...
Page 598 S5PC110_UM 2 SROM CONTROLLER 2.4.1.1 SROM Bus Width & Wait Control Register (SROM_BW, R/W, Address = 0x0000_0000) SROM_BW Description Initial State Reserved [31:24] Reserved ByteEnable5 [23] nWBE / nBE(for UB/LB) control for Memory Bank5 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0] WaitEnable5 [22]...
Page 599 S5PC110_UM 2 SROM CONTROLLER SROM_BW Description Initial State 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0] <= HADDR[22:0]) Note: When DataWidth3 is “0”, SROM_ADDR is byte base address. (Ignored this bit.) DataWidth3 [12] Data bus width control for Memory Bank3 0 = 8-bit 1 = 16-bit ByteEnable2...
Page 600 S5PC110_UM 2 SROM CONTROLLER SROM_BW Description Initial State 1 = Enables WAIT AddrMode0 Select SROM ADDR Base for Memory Bank0 0 = SROM_ADDR is Half-word base address. (SROM_ADDR[22:0] <= HADDR[23:1]) 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0] <= HADDR[22:0]) Note: When DataWidth0 is “0”, SROM_ADDR is byte base address.
Page 601 S5PC110_UM 2 SROM CONTROLLER 2.4.1.2 SROM Bank Control Register (SROM_BC: XrCSn0 ~ XrCSn2) • SROM_BC0, R/W, Address = 0xE800_0004 • SROM_BC1, R/W, Address = 0xE800_0008 • SROM_BC2, R/W, Address = 0xE800_000C • SROM_BC3, R/W, Address = 0xE800_0010 • SROM_BC4, R/W, Address = 0xE800_0014 •...
Page 602 S5PC110_UM 2 SROM CONTROLLER SROM_BCn Description Initial State Tcoh [15:12] Chip selection hold on nOE 0000 0000 = 0 clock 0001 = 1 clocks 0010 = 2 clocks 0011 = 3 clocks …………. 1100 = 12 clocks 1101 = 13 clocks 1110 = 14 clocks 1111 = 15 clocks Tcah...
Page 603: Onenand Controller
ONENAND CONTROLLER 3.1 OVERVIEW OF ONENAND CONTROLLER S5PC110 supports external 16-bit bus for OneNAND and Flex-OneNAND memory devices. The OneNAND controller supports asynchronous and synchronous read/ write bus operations. It also integrates its own dedicated DMA engine to accelerate the operations of OneNAND memory device.
Page 604: Controller Usage Expectations
S5PC110_UM 3 ONENAND CONTROLLER 3.3 CONTROLLER USAGE EXPECTATIONS The OneNAND controller is designed with the following expectations: • Supported transfer types are SINGLE/ INCR4/ INCR8/ INCR16 transactions. • Supported transfer sizes are WORD/ HALFWORD transactions for the OneNAND slave. • Supported transfer sizes are WORD transactions for the register slave.
Page 605: Functional Description Of Onenand
S5PC110_UM 3 ONENAND CONTROLLER 3.4 FUNCTIONAL DESCRIPTION OF ONENAND By default, the ARM processor directly accesses OneNAND. In addition, internal DMA engine can access OneNAND. For example, the internal DMA engine transfers data between OneNAND DataRAM and system main memory (like DRAM) without wasting the processing power of ARM processor. These additional hardware resources can be utilized to maximize the performance and minimize the usage of ARM processor for OneNAND read/ write/ copy operation.
Page 606: Clock Control
3.4.3 INITIALIZATION PROTOCOL 3.4.3.1 Power On After power on, the S5PC110 and OneNAND controller are initialized. Thereafter, OneNAND controller will automatically configure itself to work with the OneNAND flash memory devices. This automatic configuration can be achieved using one of the following: •...
Page 607: Memory Map
3 ONENAND CONTROLLER 3.5 MEMORY MAP OneNAND controller occupies 16MB address space in the system address space. The base address of OneNAND controller is configured by 0xB00000000 in S5PC110. OneNAND controller has three AHB slaves, namely: 1. OneNAND interface 2. Control registers The three AHB slaves share 16MB address space.
Page 608 S5PC110_UM 3 ONENAND CONTROLLER The corresponding commands must be issued to the device command register (Command register (device address offset: 0x1E440)). For more information about the OneNAND device memory map, refer to that Figure 3-3 shows the data path when the external AHB master accesses control registers. Table 3-1 OneNAND Controller Memory Map OneNAND Controller...
Page 609 S5PC110_UM 3 ONENAND CONTROLLER Table 3-2 OneNAND Chip #0 (nCE[0]) Address Map (If the OneNAND device is Connected to nCE[0]) OneNAND OneNAND Controller Size Controller Address (Total Description Address (End) 128KBytes) (Start) 0xB0000000 0xB00001FE 512B BootRAM Main sector0 0xB0000200 0xB00003FE 512B BootRAM Main sector1 0xB0000400...
Page 610 S5PC110_UM 3 ONENAND CONTROLLER Table 3-3 Flex-OneNAND Chip #0 (nCE[0]) Address Map (If the Flex-OneNAND device is Connected to nCE[0]) OneNAND OneNAND Size Controller Controller (Total 128KBytes) Description Address Address (Start) (End) 0xB0000000 0xB00001FE 512B BootRAM Main sector0 0xB0000200 0xB00003FE 512B BootRAM Main sector1 0xB0000400...
Page 611 S5PC110_UM 3 ONENAND CONTROLLER Figure 3-2 OneNAND Accesses (OneNAND Controller Address: 0xB0000000 ~ 0xB01FFFFF) by the External AHB Master (ARM Processor)
Page 612 S5PC110_UM 3 ONENAND CONTROLLER Figure 3-3 Control Register Accesses (OneNAND Controller Address: 0xB0600000 ~ 0xB07FFFFF) by the External AHB Master (ARM Processor) 3-10...
Page 613: Onenand Interface
S5PC110_UM 3 ONENAND CONTROLLER 3.6 ONENAND INTERFACE 3.6.1 OVERVIEW OF ONENAND INTERFACE The OneNAND interface is an AHB slave module that provides an interface for the AHB master to access OneNAND devices on the internal AHB bus of OneNAND controller. For example, 1.
Page 614: Onenand Interface Configuration
S5PC110_UM 3 ONENAND CONTROLLER To reduce the power consumption for OneNAND interface and drive the clock output to OneNAND device, the gated clock output is supported. If this feature is enabled, the OneNAND device clock is toggled only if the OneNAND device is accessed to perform read or write operation.
Page 615 S5PC110_UM 3 ONENAND CONTROLLER ONENAND_IF_CTRL Reg ister U pdate Start Read ONENAN D _IF_STAT US ORWB = 0 ? Write New Configu ratio n t o th e “System Con figu rat io n 1” Reg ister o f All th e On eNAND Devices Conn ect ed with th e On eN AND Cont ro ller Read One Dummy Half word...
Page 616 S5PC110_UM 3 ONENAND CONTROLLER Figure 3-5 ONENAND_IF_ASYNC_TIMING_CTRL (OneNAND Interface Async Timing Control) Register Update Flow 3-14...
Page 617: Onenand Device Interrupt Handling
S5PC110_UM 3 ONENAND CONTROLLER 3.6.3 ONENAND DEVICE INTERRUPT HANDLING The OneNAND interface provides two mechanisms to check the INT pin status of the OneNAND devices, namely: 1. Polling the INTD (INT Done) bits of the OneNAND Interface Status (ONENAND_IF_STATUS) register 2.
Page 618 S5PC110_UM 3 ONENAND CONTROLLER Figure 3-6 OneNAND Device INT Pin Rising Edge Wait Operations with a Polling Method Figure 3-7 OneNAND Device INT Pin Rising Edge Wait Operations with an Interrupt-Driven Method 3-16...
Page 619 S5PC110_UM 3 ONENAND CONTROLLER Figure 3-8 OneNAND Device INT Pin Rising Edge Wait Operation Timing Diagram DMA Engin 3-17...
Page 620: Dma Engine Overview
S5PC110_UM 3 ONENAND CONTROLLER 3.6.4 DMA ENGINE OVERVIEW To perform data transfer between internal AHB memory (such as OneNAND device) and external AHB memory (such as SDRAM), the internal dedicated DMA engine is embedded in the OneNAND controller. The DMA engine supports single transfer, 4-/ 8-/ 16-burst transfer with 8-/ 16-/ 32-bit data width on the AHB. In addition, it supports even unaligned transfers.
Page 621: Dma Operation
S5PC110_UM 3 ONENAND CONTROLLER 3.6.5 DMA OPERATION Set DMA control registers to configure the DMA operation. The DMA engine begins to transfer data after setting the Transfer Run (TR) bit of the DMA Transfer Command (DMA_TRANS_CMD) register to 1. The Transfer Busy (TB) bit of the DMA Transfer Status (DMA_TRANS_STATUS) register is maintained as 1 during the data transfer to indicate that the DMA engine is busy.
Page 622 S5PC110_UM 3 ONENAND CONTROLLER 3.6.5.2 DMA Operation With an Interrupt-driven Method The DMA engine asserts system interrupt signal for the transfer done or the transfer error event DMA Start Read INTC_DMA_MASK DMTD = 0 && DMTE = 0 ? ARM_IRQ = 1 ? Write 0 to both DMTD and ARM Processor Jumps to the Write 1 to TDC bit of...
Page 623: I/O Interface
S5PC110_UM 3 ONENAND CONTROLLER 3.7 I/O INTERFACE Signal Description Type Address Bus outputs, during memory read/ write Xm0ADDR ADDR[15:0] muxed address phase [15:0] Data Bus outputs address during memory read/ write address phase, inputs data during memory read data Xm0DATA DQ[15:0] muxed phase and outputs data during memory write data...
Page 624: Register Description
S5PC110_UM 3 ONENAND CONTROLLER 3.8 REGISTER DESCRIPTION 3.8.1 REGISTER MAP Register Address Description Reset Value ONENAND_IF_CTRL 0xB060_0100 OneNAND Interface Control register 0x80004000 0x00004000 ONENAND_IF_CMD 0xB060_0104 OneNAND Interface Command 0x00000000 register ONENAND_IF_ASYNC_TIMI 0xB060_0108 OneNAND Interface Async. Timing 0x00003415 NG_CTRL Control register ONENAND_IF_STATUS 0xB060_010C OneNAND Interface Status Register...
Page 625: Onenand Interface Register
S5PC110_UM 3 ONENAND CONTROLLER 3.8.2 ONENAND INTERFACE REGISTER 3.8.2.1 OneNAND Interface Control Register (ONENAND_IF_CTRL, R/W, Address = 0xB060_0100) ONENAND_ Description Initial State IF_CTRL [31] 1b or 0b Mux or Demux OneNAND Type Select OneNAND interface supports both Demux and Mux type OneNAND devices.
Page 626 S5PC110_UM 3 ONENAND CONTROLLER ONENAND_ Description Initial State IF_CTRL This bit is used to select the burst read/ write latency between 3 clocks and 7 clocks. BRWL (burst read write latency) bits specify the access latency in the burst read/ write transfer for the initial access. Note that these bits are valid only for the synchronous read/ write operation.
Page 627 S5PC110_UM 3 ONENAND CONTROLLER Figure 3-12 ONENAND Interface Synchronous Read Timing C LK 2x (I nternal) C LK nC E nAVD 1 C lock 1 C lock BL C locks 3 C locks Valid AD DR A ddress BR WL C locks 1-st 2-nd 3-rd...
Page 628 S5PC110_UM 3 ONENAND CONTROLLER 3.8.2.2 OneNAND Interface Command Register (ONENAND_IF_CMD, W, Address = 0xB060_0104) ONENAND_ Description Initial State IF_CMD [31:18] Reserved INTC [17:16] OneNAND INT Done Clear When this bit is set to 1, the INTD (OneNAND INT done) bit flag of the OneNAND Interface Status Register (ONENAND_IF_STATUS) is cleared to 0.
Page 629 S5PC110_UM 3 ONENAND CONTROLLER 3.8.2.3 OneNAND Interface Async Timing Control Register (ONENAND_IF_ASYNC_TIMING_CTRL, R/W, Address = 0xB060_0108) ONENAND_IF_ ASYNC_TIMING Description Initial State _CTRL [31:16] Reserved [15:12] nWE High Length nWE signal is held to high for WHL clock time at OneNAND asynchronous read/ write execution.
Page 630 S5PC110_UM 3 ONENAND CONTROLLER Async. Read D ata Sampling Timing C LK 2x (I nternal) C LK nOE H igh Length nC E Clocks nAVD 1 C lock 1 C lock 1 C lock (nOE Low Length + 2) C locks AD D R V alid Address Valid R ead Dat a...
Page 631 S5PC110_UM 3 ONENAND CONTROLLER 3.8.2.4 OneNAND Interface Status Register (ONENAND_IF_STATUS, R, Address = 0xB060_010C) ONENAND_ Description Initial State IF_STATUS [31:24] Reserved [23:18] Reserved 111111b INTD [17:16] OneNAND INT Done This status is used to check whether the OneNAND command execution is complete or not. Check whether the OneNAND INT pin’s rising edge has been occurred or not after issuing a command to the OneNAND to notify command execution completion.
Page 632: Dma Control Registers
S5PC110_UM 3 ONENAND CONTROLLER 3.8.3 DMA CONTROL REGISTERS 3.8.3.1 DMA Source Address Register (DMA_SRC_ADDR, R/W, Address = 0xB060_0400) DMA_SRC_ADDR Description Initial State [31:0] 00000000h Source Address Source address on the AHB for the DMA operation. The start address for the DMA engine to perform read operation.
Page 633 S5PC110_UM 3 ONENAND CONTROLLER DMA_SRC_CFG Description Initial State memory address should be the multiple of the HSIZE (data width). If this address alignment condition is not satisfied, the actual data width on the AHB during the DMA transfer will be smaller than the access size specified in these bits.
Page 634 S5PC110_UM 3 ONENAND CONTROLLER 3.8.3.4 DMA Destination Configuration Register (DMA_DST_CFG, R/W, Address = 0xB060_040C) DMA_DST_CFG Description Initial State [31:19] Reserved [18:16] 100b Destination Burst Length Burst length during the destination memory access on the AHB for the DMA operation. This burst length is valid only when the memory address is aligned.
Page 635 S5PC110_UM 3 ONENAND CONTROLLER 3.8.3.5 DMA Transfer Size Register (DMA_TRANS_SIZE, R/W, Address = 0xB060_0414) DMA_TRANS_ Description Initial State SIZE [31:24] Reserved [23:0] 000000h Transfer Size The number of bytes to be transferred to the AHB by the DMA engine. Transfer size must be less than 16MBytes. If the DMA source or destination address is in the OneNAND interface slave address space, TS (Transfer Size) must be the multiple of 2 because OneNAND interface slave does NOT...
Page 636 S5PC110_UM 3 ONENAND CONTROLLER 3.8.3.7 DMA Transfer Status Register (A_TRANS_STATUS, R, Address = 0xB060_041C) A_TRANS_ Description Initial State STATUS [31:19] Reserved [18] Transfer Done This status is used to check whether the DMA transfer is complete or not. After the DMA transfer is successfully completed, TD bit is set to 1.
Page 637 S5PC110_UM 3 ONENAND CONTROLLER 3.8.3.8 DMA Transfer Direction Register (DMA_TRANS_DIR, R/W, Address = 0xB060_0420) DMA_TRANS_ Description Initial State [31:1] Reserved TDIR Transfer Direction This bit specifies the transfer direction of the DMA operation between the OneNAND controller’s internal AHB memory and the OneNAND controller’s external AHB memory.
Page 638: Interrupt Controller Registers
S5PC110_UM 3 ONENAND CONTROLLER 3.8.4 INTERRUPT CONTROLLER REGISTERS Interrupt controller registers can be classified into following four register types: 1) interrupt pending registers, 2) interrupt status registers, 3) interrupt mask registers, and 4) interrupt clear registers. Each interrupt pending register represents the raw status of the interrupt sources such as DMA transfer done, DMA transfer error, and OneNAND INT pin done.
Page 639 S5PC110_UM 3 ONENAND CONTROLLER 3.8.4.2 Interrupt Controller OneNAND Clear Register (INTC_ONENAND_CLR, W, Address = 0xB060_1008) INTC_ONENAND Description Initial State _CLR [31:2] Reserved OCINTD [1:0] OneNAND Clear INT Done When this bit is set to 1, the corresponding OSINTD (OneNAND status INT done) bit flag of the Interrupt Controller OneNAND Status Register (INTC_ONENAND_STATUS) in the interrupt controller is cleared to 0.
Page 640 S5PC110_UM 3 ONENAND CONTROLLER 3.8.4.5 Interrupt Controller DMA Pending Register (INTC_DMA_PEND, R, Address = 0xB060_1044) INTC_DMA_PEND Description Initial State [31:25] Reserved DPTD [24] DMA Pending Transfer Done This bit is the exact copy of the TD (transfer done) bit flag of the DMA Status Register (DMA_STATUS) [13:17] Reserved...
Page 641 S5PC110_UM 3 ONENAND CONTROLLER 3.8.4.8 Interrupt Controller OneNAND Status Register (INTC_ONENAND_STATUS, R, Address = 0xB060_1068) INTC_ONENAND_ Description Initial State STATUS [31:2] Reserved OSINTD [1:0] OneNAND Status INT Done This bits are logical AND operation result of OPINTD (OneNAND pending INT done) bit flags of the interrupt controller OneNAND pending register (INTC_ONENAND_PEND) and inverse of OMINTD (OneNAND mask INT done) bit flag of the Interrupt Controller...
Page 642: Nand Flash Controller
NAND flash and execute the main code on DRAM. The boot code in S5PC110 can be executed on external NAND flash. It will copy NAND flash data to DRAM. To validate the NAND flash data, S5PC110 comprises of hardware Error Correction Code (ECC). After the NAND flash content is copied to DRAM, main program will be executed on DRAM.
Page 643: Block Diagram
S5PC110_UM 4 NAND FLASH CONTROLLER 4.2.1 BLOCK DIAGRAM nFCE ECC Gen. NAND FLASH Interface Slave I/F Control & R/nB State Machine I/O0 - I/O7 Figure 4-1 NAND Flash Controller Block Diagram 4.2.2 NAND FLASH MEMORY TIMING TACLS TWRPH0 TWRPH1 HCLK CLE / ALE DATA COMMAND / ADDRESS...
Page 644 S5PC110_UM 4 NAND FLASH CONTROLLER TWRPH0 TWRPH1 HCLK nWE / nRE DATA DATA Figure 4-3 nWE and nRE Timing (TWRPH0=0, TWRPH1=0)
Page 645: Software Mode
S5PC110_UM 4 NAND FLASH CONTROLLER 4.3 SOFTWARE MODE S5PC110 supports only software mode access. Use this mode to access NAND flash memory. The NAND flash controller supports direct access to interface with the NAND flash memory. • Writing to the command register (NFCMMD) specifies the NAND Flash Memory command cycle •...
Page 646: 4-/ 8-/ 12-/ 16-Bit Ecc
S5PC110_UM 4 NAND FLASH CONTROLLER 4.3.2 1-/ 4-/ 8-/ 12-/ 16-BIT ECC NAND flash controller supports 1-/ 4-/ 8-/ 12-/ 16-bit ECC. For 1-bit ECC, NAND flash controller comprises ECC modules for main and spare (meta) data. Main data ECC module generates ECC parity code for 2048 bytes (maximum) data/ message length, whereas spare (meta) data ECC module generates ECC Parity code for 32 bytes (maximum).
Page 647: Byte 1-Bit Ecc Parity Code Assignment Table
S5PC110_UM 4 NAND FLASH CONTROLLER 4.3.3 2048 BYTE 1-BIT ECC PARITY CODE ASSIGNMENT TABLE DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 MECCn_0 ~P64 ~P64’ ~P32 ~P32’ ~P16 ~P16’ ~P8’ MECCn_1 ~P1024 ~P1024’ ~P512 ~P512’ ~P256 ~P256’ ~P128 ~P128’ MECCn_2 ~P4’...
Page 648: 1-Bit Ecc Programming Guide
S5PC110_UM 4 NAND FLASH CONTROLLER 4.3.6 1-BIT ECC PROGRAMMING GUIDE 1. To use SLC ECC in software mode, reset the ECCType to ‘0’ (enable SLC ECC)‘. ECC module generates ECC parity code for all read / write data when MainECCLock (NFCON[7]) and SpareECCLock (NFCON[6]) are unlocked(‘0’).
Page 649: 4-Bit Ecc Programming Guide (Encoding)
S5PC110_UM 4 NAND FLASH CONTROLLER 4.3.7 4-BIT ECC PROGRAMMING GUIDE (ENCODING) 1. To use 4-bit ECC in software mode, set the MsgLength to 0(512-byte message length) and the ECCType to “10”(enable 4bit ECC). ECC module generates ECC parity code for 512-byte write data. To reset ECC value write the InitMECC (NFCONT[5]) bit as ‘1’...
Page 650: 4-Bit Ecc Programming Guide (Decoding)
S5PC110_UM 4 NAND FLASH CONTROLLER 4.3.8 4-BIT ECC PROGRAMMING GUIDE (DECODING) 1. To use 4-bit ECC in software mode, set the MsgLength to 0 (512-byte message length) and the ECCType to “10” (enable 4-bit ECC). ECC module generates ECC parity code for 512-byte read data. Therefore, to reset ECC value write the InitMECC (NFCONT[5]) bit as ‘1’...
Page 651: 8-Bit / 12-Bit / 16-Bit Ecc Programming Guide (Encoding)
S5PC110_UM 4 NAND FLASH CONTROLLER 4.3.9 8-BIT / 12-BIT / 16-BIT ECC PROGRAMMING GUIDE (ENCODING) 1. To use 8/ 12/ 16-bit ECC in software mode, set the MsgLength(NFECCCONF[25:16]) to 511(512byte message length) and the ECCType to “001/100/101”(enable 8/12/16-bit ECC, respectively). ECC module generates ECC parity code for 512 byte write data.
Page 652: 8/12/16-Bit Ecc Programming Guide (Decoding)
S5PC110_UM 4 NAND FLASH CONTROLLER 4.3.10 8/12/16-BIT ECC PROGRAMMING GUIDE (DECODING) 1. To use 8/ 12/ 16-bit ECC in software mode, set the MsgLength(NFECCCONF[25:16] to 511(512-byte message length) and the ECCType to “001/100/101”(enable 8/12/16-bit ECC, respectively). ECC module generates ECC parity code for 512-byte read data. Therefore, you must reset ECC value by writing the InitMECC (NFECCCONT[2]) bit as ‘1’, and clear the MainECCLock(NFCONT[7]) bit to ‘0’(Unlock) before read data.
Page 653: Ecc Parity Conversion Code Guide For 8/12/16-Bit Ecc
S5PC110_UM 4 NAND FLASH CONTROLLER 4.3.11 ECC PARITY CONVERSION CODE GUIDE FOR 8/12/16-BIT ECC The ECC parity conversion codes are there to fix errors, which occur when reading a free page. Free page means the page erased. The 8/ 12/ 16-bit ECC modules support variable message size for meta data stored in spare area.
Page 654: Lock Scheme For Data Protection
S5PC110_UM 4 NAND FLASH CONTROLLER 4.3.12 LOCK SCHEME FOR DATA PROTECTION NFCON provides a lock scheme to protect data stored in external NAND Flash memories from malicious program. For this scheme, the NFSBLK and NFEBLK registers are used to provide access control methods; only the memory area between NFSBLK and NFEBLK is erasable and programmable, but the read access is available to whole memory area.
Page 655: I/O Description
S5PC110_UM 4 NAND FLASH CONTROLLER 4.4 I/O DESCRIPTION Signal Description Type Xm0DATA Input / Output Address / Data Bus Xm0DATA muxed Xm0FRnB[3:0] Input Ready and Busy Xm0FRnB muxed Xm0FCLE Output Command Latch Enable Xm0FCLE muxed Xm0FALE Output Address Latch Enable Xm0FALE muxed Xm0CSn[2:5]...
Page 656: Register Description
S5PC110_UM 4 NAND FLASH CONTROLLER 4.5 REGISTER DESCRIPTION 4.5.1 REGISTER MAP Register Address Description Reset Value NFCONF 0xB0E0_0000 Configuration Register 0x0000_1000 NFCONT 0xB0E0_0004 Control Register 0x00C1_00C6 NFCMMD 0xB0E0_0008 Command Register 0x0000_0000 NFADDR 0xB0E0_000C Address Register 0x0000_0000 NFDATA 0xB0E0_0010 Data Register 0x0000_0000 NFMECCD0 0xB0E0_0014...
Page 657 S5PC110_UM 4 NAND FLASH CONTROLLER Register Address Description Reset Value NFECCERL3 0xB0E2_00CC ECC error byte location3 register 0x0000_0000 NFECCERL4 0xB0E2_00D0 ECC error byte location4 register 0x0000_0000 NFECCERL5 0xB0E2_00D4 ECC error byte location5 register 0x0000_0000 NFECCERL6 0xB0E2_00D8 ECC error byte location6 register 0x0000_0000 NFECCERL7 0xB0E2_00DC...
Page 658: Nand Flash Interface And 1 / 4-Bit Ecc Registers
S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.2 NAND FLASH INTERFACE AND 1 / 4-BIT ECC REGISTERS 4.5.2.1 Nand Flash Configuration Register (NFCONF, R/W, Address = 0xB0E0_0000) NFCONF Description Initial State Reserved [31:26] Reserved MsgLength [25] 0 = 512 byte Message Length 1 = 24 byte Message Length ECCType0 [24:23]...
Page 659 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.2.2 Control Register (NFCONT, R/W, Address = 0xB0E0_0004) NFCONT Description Initial State Reserved [31:24] Reserved Reg_nCE3 [23] NAND Flash Memory nRCS[3] signal control 0 = Force nRCS[3] to low (Enable chip select) 1 = Force nRCS[3] to High (Disable chip select) Reg_nCE2 [22] NAND Flash Memory nRCS[2] signal control...
Page 660 S5PC110_UM 4 NAND FLASH CONTROLLER NFCONT Description Initial State MECCLock Lock Main area ECC generation 0 = Unlock Main area ECC 1 = Lock Main area ECC Main area ECC status register is NFMECC0/NFMECC1(0xB0E0_0034/0xB0E0_0038), SECCLock Lock Spare area ECC generation. 0 = Unlock Spare ECC 1 = Lock Spare ECC Spare area ECC status register is NFSECC(0xB0E0_003C),...
Page 661 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.2.5 Data Register (NFDATA, R/W, Address = 0xB0E0_0010) NFDATA Description Initial State NFDATA [31:0] NAND Flash read/ program data value for I/O 0x00000000 Note: For more information, refer to 4.3.1 Data Register in page 4-4. Configuration 4.5.2.6 Main Data Area ECC Register (NFMECCD0, R/W, Address = 0xB0E0_0014) NFMECCD0...
Page 662 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.2.8 Only Word Access is Allowed Spare Area ECC Register (NFSECCD, R/W, Address = 0xB0E0_001C) NFSECCD Description Initial State Reserved [31:24] Reserved 0x00 SECCData1 [23:16] 0xFF Note: In software mode, read this register when you need to read 2 ECC value from NAND Flash memory Reserved...
Page 663 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.2.11 NFCON Status Register (NFSTAT, R/W, Address = 0xB0E0_0028) NFSTAT Description Initial State Flash_RnB_GRP [31:28] The status of RnB[3:0] input pin. 0 = NAND Flash memory busy 1 = NAND Flash memory ready to operate RnB_TransDetect [27:24] When RnB[3:0] low to high transition occurs, this bit is set and an...
Page 664 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.2.12 ECC0/1 Error Status Register (NFECCERR0, R, Address = 0xB0E0_002C) • When ECC Type is 1-bit ECC NFECCERR0 Description Initial State Reserved [31:25] Reserved 0x00 ECCSDataAddr [24:21] In spare area, Indicates which number data is error ECCSBitAddr [20:18] In spare area, Indicates which bit is error...
Page 665 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.2.13 ECC0/1 Error Status Register (NFECCERR1, R, Address = 0xB0E0_0030) • When ECC Type is 4-bit ECC NFECCERR1 Description Initial State Reserved [31:26] Reserved 0x00 MLCErrLocation4 [25:16] 0x00 Error byte location of 4 bit error Reserved [15:10] Reserved...
Page 666 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.2.15 Main data area ECC0 status Register (NFMECC1, R, Address = 0xB0E0_0038) • When ECCType is 4-bit ECC NFMECC1 Description Initial State Reserved [31:24] Reserved 0x00 7th Parity [23:16] 7th Check Parity generated from main area (512-byte) 0x00 6th Parity [15:8]...
Page 667: Ecc Registers For 8, 12 And 16-Bit Ecc
S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.3 ECC REGISTERS FOR 8, 12 AND 16-BIT ECC 4.5.3.1 Nand Flash ECC Configuration Register (NFECCCONF, R/W, Address = 0xB0E2_0000) NFECCCONF Description Initial State Reserved [31] Reserved Reserved [28] Reserved MsgLength [25:16] The ECC message size. For 512-byte message, you should set 511.
Page 668 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.3.3 Nand Flash ECC Status Register (NFECCSTAT, R/W, Address = 0xB0E2_0030) NFECCSTAT Description Initial State ECCBusy [31] Indicates the 8-bit ECC decoding engine is searching whether a error exists or not 0 = Idle 1 = Busy Reserved [30] Reserved...
Page 669 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.3.5 Nand Flash ECC Parity code for Page Program Register (NFECCPRGECC*, R, Address = 0xB0E2_0090 ~ 0xB0E2_00A8) NFECCPRGECC0 Description Initial State 4th Parity [31:24] 4th Check Parity for page program from main area 0x00 3rd Parity [23:16] 3rd Check Parity for page program from main area 0x00...
Page 670 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.3.6 MLC ECC Error Byte Location Status Register (NFECCERL0~7, R, Address = 0xB0E2_00C0 ~ 0xB0E2_00DC) NFECCERL0 Description Initial State Reserved [31:26] Reserved ErrByteLoc2 [25:16] 0x000 Error byte location of 2 bit error Reserved [15:10] Reserved ErrByteLoc1 [9:0] 0x000...
Page 671 S5PC110_UM 4 NAND FLASH CONTROLLER Reserved [31:26] Reserved ErrByteLoc16 [25:16] 0x000 Error byte location of 16 bit error Reserved [15:10] Reserved ErrByteLoc15 [9:0] 0x000 Error byte location of 15 bit error NOTE: These values are updated when DecodeDone (NFECCSTAT[24]) is set (‘1’). 4.5.3.7 MLC ECC Error Patten Register (NFECCERP0~3, R, Address = 0xB0E2_00F0 ~ 0xB0E2_00FC) NFECCERP0 Description...
Page 672 S5PC110_UM 4 NAND FLASH CONTROLLER 4.5.3.8 ECC Parity Conversion Register (NFECCCONECC0~6, R/W, Address = 0xB0E2_0110 ~ 0xB0E2_0128) NFECCCONECC0 Description Initial State [31:24] 0x00 Conversion Code ECC Parity conversion code [23:16] 0x00 Conversion Code ECC Parity conversion code [15:8] 0x00 Conversion Code ECC Parity conversion code [7:0] 0x00...
Page 673: Compact Flash Controller
S5PC110_UM 5 COMPACT FLASH CONTROLLER COMPACT FLASH CONTROLLER 5.1 OVERVIEW OF COMPACT FLASH CONTROLLER A Compact Flash Controller (CFC) connects seamlessly to the AHB Bus as a Bus slave and AHB Master. The CFC subsystem recognizes AHB Bus transactions that target the compact flash card. The Master Interface initiates compact flash card requests to the CFC block requester interface.
Page 674: Block Diagram Of Compact Flash Controller
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.3 BLOCK DIAGRAM OF COMPACT FLASH CONTROLLER FIFO Master Interface Device Internal Control Logic Interrupt Slave Control ATA Controller Figure 5-1 Block Diagram of Compact Flash Controller 5.4 FUNCTIONAL DESCRIPTION The ATAPI controller is compatible with the ATA/ATAPI-5 standard. This mode allows I/O operations to the task file and data registers.
Page 675: True Ide Mode Pio/ Pdma Timing Diagram
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.5 TRUE IDE MODE PIO/ PDMA TIMING DIAGRAM The PIO transfer protocol supports 8-bit register access in driver and 16-bit PIO data access. If PIO mode 3 or 4 is the currently selected mode of operation, both hosts and devices support ATA_IORDY. The defines the Figure 5-2 relationships between host and device interface signals for data and registers transfer.
Page 676 S5PC110_UM 5 COMPACT FLASH CONTROLLER Table 5-1 describes the timing parameters of PIO modes. Table 5-1 shows the timing cycle of the true IDE PIO mode, if ATA controller is in the ATA_TRANS state. Figure 5-2 The figure indicates various timing parameters. Timing ‘t1’ indicates the time between address valid and IORD/IOWR asserted.
Page 677: Ata_Pio_Time Register Setting Example (In Case Of Data Transfer)
S5PC110_UM 5 COMPACT FLASH CONTROLLER Table 5-1 Timing Parameter Each PIO Mode Register Transfer MODE0 MODE1 MODE2 MODE3 MODE4 (70, --) (50, --) (30, --) (30, --) (25, --) (290, --) (290, --) (290, --) (80, --) (70, --) tEOC (240, --) (43, --) (10, --)
Page 678: Flowchart For Pio Read / Write
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.6 FLOWCHART FOR PIO READ / WRITE Figure 5-3 Flowchart for Read / Write in PIO Class...
Page 679: True Ide Mdma Mode Timing Diagram
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.7 TRUE IDE MDMA MODE TIMING DIAGRAM The ATAPI MDMA streams data continuously across the ATA interface between the host and the target device. This transfer class allows either the driver or host to pause or terminate the data flow. To support various transfer speed classes, the CPU programs appropriate timing parameters.
Page 680: Ata_Mdma_Time Register Setting Example
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.7.1 ATA_MDMA_TIME REGISTER SETTING EXAMPLE The “td” minimum time is 215ns in the system clock 100MHz (10ns). It gives 21.5; “td” divided by 10ns. This case has residual, assigning quotient (21) to the dma_td[3:0]. If it has no residual, assign the quotient minus 1 at dma_td[3:0].
Page 681: True Ide Udma Mode Timing Diagram
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.8 TRUE IDE UDMA MODE TIMING DIAGRAM The Ultra-DMA (UDMA) is a fast DMA protocol which supports six timing modes (mode 0 ~ 5). Mode 5 is the fastest; it operates at 100MHz. This ATAPI host controller supports upto mode 4. It operates at 66MHz. Both host and device driver perform CRC check during UDMA burst transfer.
Page 682 S5PC110_UM 5 COMPACT FLASH CONTROLLER DMARQ DMACK DIOW DIOR tACKENV tACKENV CS0,CS1, DA[2:0] IORDY tDVS tDVH DD[15:0 ] or DD[7:0] Figure 5-6 UDMA - In Operation (Terminated by Host) DMARQ DMACK tACKENV tACKENV DIOW DIOR tACKENV CS0,CS1, DA[2:0] IORDY tDVS tDVH tDVS tDVH...
Page 683 S5PC110_UM 5 COMPACT FLASH CONTROLLER DMARQ DMACK DIOW tACKENV DIOR CS0,CS1, DA[2:0] IORDY tDVS tDVH DD[15:0 ] or DD[7:0] Figure 5-8 UDMA - Out Operation (Terminated by Host) Table 5-3 Timing Parameter Each UDMA Mode UDMA mode UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4...
Page 684: Ata_Udma_Time Register Setting Example
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.8.1 ATA_UDMA_TIME REGISTER SETTING EXAMPLE The “tackenv” minimum time is 20ns in the system clock of 100MHz (10ns). It gives 2; “tackenv” divided by 10ns. This case has no residual, therefore the udma_tackenv[3:0] assigns 1 which is 2 minus 1. If it has residual, assign the quotient at udma_tackenv[3:0].
Page 685: Transfer State Abort
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.9 TRANSFER STATE ABORT The PIO, PDMA, MDMA or UDMA checks for abort or stop transfer state after completing one full cycle of the finite state machine (FSM). The FSM transition from IDLE state happens if ATA transfer state is in ATA_TRANS. The FSM continues the cycle while the abort is asserted.
Page 686: I/O Description
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.10 I/O DESCRIPTION Signal Description Type CSn0 Device chip selection signal XmsmCSn muxed To select the control block registers CSn1 Device chip selection signal XmsmWEn muxed To select the command block registers DA[2:0] register address signals XmsmADDR[2:0] muxed DD_RD[15:0]...
Page 687: Register Description
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11 REGISTER DESCRIPTION 5.11.1 REGISTER MAP Register Address Description Reset Value ATA_CONTROL 0xE820_0000 Specifies the ATA enable and clock down 0x00000002 status ATA_STATUS 0xE820_0004 Specifies the ATA status 0x00000008 ATA_COMMAND 0xE820_0008 Specifies the ATA command 0x00000000 ATA_SWRST 0xE820_000C...
Page 688 S5PC110_UM 5 COMPACT FLASH CONTROLLER Register Address Description Reset Value ATA_PIO_LHR 0xE820_0068 Specifies the ATA PIO device LBA high 0x00000000 register ATA_PIO_DVR 0xE820_006C Specifies the ATA PIO device register 0x00000000 ATA_PIO_CSD 0xE820_0070 Specifies the ATA PIO device command/ 0x00000000 status register ATA_PIO_DAD 0xE820_0074 Specifies the ATA PIO device control/...
Page 689 S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.1.1 ATA Control Register (ATA_CONTROL, R/W, Address = 0xE820_0000) ATA_CONTROL Description Initial State Reserved [31:2] Reserved clk_down_ready Status for clock down This bit is asserted in idle state if ATA_CONTROL bit [0] is zero. 0 = Not ready for clock down 1 = Ready for clock down ata_enable Enables ATA...
Page 690: Ata Command Register (Ata_Command, R/W, Address = 0Xe820_0008)
S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.2 ATA COMMAND REGISTER (ATA_COMMAND, R/W, ADDRESS = 0XE820_0008) ATA_COMMAND Description Initial State Reserved [31:2] Reserved xfr_command [1:0] ATA transfer command Four command types (START, STOP, ABORT and CONTINUE) are supported for data transfer control. The “START”...
Page 691 S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.2.1 ATA Software Reset (ATA_SWRST, R/W, Address = 0xE820_000C) ATA_SWRST Description Initial State Reserved [31:1] Reserved ata_swrst Software reset for the ATAPI host 0 = No reset 1 = Resets device registers and all registers of ATAPI host controller except CPU interface registers.
Page 692 S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.2.3 ATA Interrupt Mask Register (ATA_IRQ_MASK, R/W, Address = 0xE820_0014) ATA_IRQ_MASK Description Initial State Reserved [31:6] Reserved mask_mdma_hold_int 0 = Mask mdma_hold_int; Disable 1 = Unmask mdma_hold_int; Enable mask_sbut_empty_int 0 = Mask sbut_empty_int; Disable 1 = Unmask sbuf_empty_int; Enable mask_tbuf_full_int 0 = Mask tbuf_full_int;...
Page 693 S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.2.4 ATA Configuration Register (ATA_CFG, R/W, Address = 0xE820_0018) ATA_CFG Description Initial State Reserved [31] Reserved (This field should be 0x1) Reserved [30:13] Reserved dma_mode [12] Determines whether DMA is normal DMA 0 = Normal DMA mode 1 = Reserved.
Page 694 S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.2.5 ATA Multi_word DMA Timing (ATA_MDMA_TIME, R/W, Address = 0xE820_0028) ATA_MDMA_TIME Description Initial State Reserved [31:20] Reserved dma_teoc [19:12] DMA timing parameter, Teoc, end of cycle time 0x2C dma_t2 [11:4] DMA timing parameter, tD, DIOR/DIOWn pulse width 0x23 dma_t1 [3:0]...
Page 695 S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.2.8 ATA Transfer Count Number (ATA_XFR_NUM, R/W, Address = 0xE820_0034) ATA_XFR_NUM Description Initial State xfr_num [31:1] Data transfer number. 0x00000000 To transfer 1-sector (512-byte), you should set 32’h1ff. Reserved Reserved 5.11.2.9 ATA Current Transfer Count (ATA_XFR_CNT, R, Address = 0xE820_0038) ATA_XFR_CNT Description Initial State...
Page 696 S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.2.13 Size of Source Buffer (ATA_SBUF_SIZE, R/W, Address = 0xE820_0048) ATA_SBUF_SIZE Description Initial State src_buffer_size [31:5] Size of source buffer (32byte unit) 0x0000000 This should be set to “size_of_data_in_bytes – 1”. For example, to transfer 1-sector (512-byte, 32’h200), you should set 32’h1FF ( = 32’h200 –...
Page 697 S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.2.19 ATA PIO Device LBA Low Register (ATA_PIO_LLR, R/W, Address = 0xE820_0060) ATA_PIO_LLR Description Initial State Reserved [31:8] Reserved pio_dev_llr [7:0] 8-bit PIO device LBA low (command block) register 0x00 5.11.2.20 ATA PIO Device LBA Middle Register (ATA_PIO_LMR, R/W, Address = 0xE820_0064) ATA_PIO_LMR Description Initial State...
Page 698 S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.2.25 ATA PIO Data Ready Register (ATA_PIO_READY, R, Address = 0xE820_0078) ATA_PIO_READY Description Initial State Reserved [31:2] Reserved dev_acc_ready Indicates whether host can start access to device register 0 = Not ready to start access ATA device register 1 = Ready to start access ATA device register pio_data_ready Indicates whether data is valid in ATA_PIO_DATA...
Page 699 S5PC110_UM 5 COMPACT FLASH CONTROLLER 5.11.2.28 ATA FIFO Status Register (ATA_FIFO_STATUS, R, Address = 0xE820_0084) ATA_FIFO_STATUS Description Initial State Reserved [31] Reserved ata_state [30:28] 0 = ATA_IDLE 0x0000 1 = ATA_TRANS 2 = ATA_PAUSE 3 = ATA_PAUSE2 4 = ATA_ABORT pio_state [27:26] 2’b00 = IDLE 2’b01 = T1...
Page 700: External Bus Interface
6.1 OVERVIEW OF EXTERNAL BUS INTERFACE The External Bus Interface (EBI) is used as a peripheral in S5PC110. It relies on memory controller to release external requests for external bus when the memory controller is idle, since it has no knowledge of when memory access will begin or complete.
Page 701: Block Diagram Of Memory Interface Through Ebi
S5PC110_UM 6 EXTERNAL BUS INTERFACE 6.3 BLOCK DIAGRAM OF MEMORY INTERFACE THROUGH EBI Figure 6-1 Memory Interface Through EBI...
Page 702: Clock Scheme Of Memory Controllers And Ebi
S5PC110_UM 6 EXTERNAL BUS INTERFACE 6.4 CLOCK SCHEME OF MEMORY CONTROLLERS AND EBI Figure 6-2 Clock Scheme of Memory Controllers and EBI NOTE: The OneNAND Clock selection register name in Section 2-3, “Clock Controller” is OneNAND_SEL (OneNAND_Async). The register address is 0xE010_0200 (CLK_SRC0[28]).
Page 703 Section 6...
Page 704 Table of Contents DMA Controller ...................1-1 1.1 Overview of DMA Controller ........................1-1 1.1.1 Key Features of DMA Controller....................... 1-2 1.2 Register Description..........................1-5 1.2.1 Register Map ............................ 1-5 1.3 Instruction............................... 1-25 1.3.1 Key Instruction ..........................1-26 1.3.2 USAGE Model ..........................1-28...
Page 705 List of Figures Figure Title Page Number Number Figure 1-1 Two DMA Tops ..........................1-1...
Page 706 List of Tables Table Title Page Number Number Table 1-1 DMA Request Mapping Table......................1-2 Table 1-2 DMA_mem Register Summary ......................1-5 Table 1-3 DMA_peri0 Register Summary ......................1-9 Table 1-4 DMA_peri0 Register Summary ......................1-13 Table 1-5 Instruction Syntax Summary ......................1-25...
Page 707: Dma Controller
DMA CONTROLLER 1.1 OVERVIEW OF DMA CONTROLLER S5PC110 supports two Direct Memory Access (DMA) tops: one for Memory-to-Memory (M2M) transfer (DMA_mem) and other for Peripheral-to-memory transfer and vice-versa (DMA_peri). The M2M DMA top consists of PL330 and some logics. On the other hand, Peri DMA top consists of two PL330s (DMA0 and DMA1) and dma_map.
Page 708: Key Features Of Dma Controller
S5PC110_UM 1 DMA CONTROLLER 1.1.1 KEY FEATURES OF DMA CONTROLLER The key features of DMA Controller are listed below as reference for DMA and for writing DMA assembly code. Key Features DMA_mem DMA_peri Supports Data Size Up to double word (64-bit) Up to word (32-bit) Word transfer: Up to 8 burst Supports Burst Size...
Page 709 S5PC110_UM 1 DMA CONTROLLER Module DMA Request Category Service Module Reserved UART3_TX UART3_RX UART2_TX System UART2_RX UART1_TX UART1_RX UART0_TX UART0_RX Peri DMA0 Reserved Reserved Reserved Reserved Others SPDIF by only DMA0 Reserved AC_PCMout AC_PCMin AC_MICin SPI1_TX SPI1_RX SPI0_TX Audio and SPI SPI0_RX Reserved Reserved...
Page 710 S5PC110_UM 1 DMA CONTROLLER Module DMA Request Category Service Module UART2_RX UART1_TX UART1_RX UART0_TX UART0_RX DMA_mem Security by M2M DMA only When PDMA0 or PDMA1 are enabled, the CLK_GATE_IP2[8] at SYSCON must be set to 1. Caution:...
Page 711: Register Description
Most Special Function Registers (SFRs) are read-only. The main role of SFR is to check the PL330 status. There are many SFRs for PL330. In this section, only S5PC110-specific SFRs are explained. For more information, refer to Chapter 3, “PL330 TRM”.
Page 712 S5PC110_UM 1 DMA CONTROLLER Register Address Description Reset Value 0xFA20_0060- Reserved 0xFA20_00FC Channel Status Registers. For more information, refer to page 3-24 of “PL330 TRM”. 0xFA20_0100 Specifies the Channel Status for DMA Channel 0. 0xFA20_0108 Specifies the Channel Status for DMA Channel 1. 0xFA20_0110 Specifies the Channel Status for DMA Channel 2.
Page 713 S5PC110_UM 1 DMA CONTROLLER Register Address Description Reset Value DA_3 0xFA20_0464 Specifies the Destination Address for DMA Channel DA_4 0xFA20_0484 Specifies the Destination Address for DMA Channel DA_5 0xFA20_04A4 Specifies the Destination Address for DMA Channel DA_6 0xFA20_04C4 Specifies the Destination Address for DMA Channel DA_7 0xFA20_04E4 Specifies the Destination Address for DMA Channel...
Page 714 S5PC110_UM 1 DMA CONTROLLER Register Address Description Reset Value Reserved 0xFA20_0434- Reserved 0xFA20_043C Reserved 0xFA20_0454- Reserved 0xFA20_045C Reserved 0xFA20_0474- Reserved 0xFA20_047C Reserved 0xFA20_0494- Reserved 0xFA20_049C Reserved 0xFA20_04B4- Reserved 0xFA20_04BC Reserved 0xFA20_04D4- Reserved 0xFA20_04DC Reserved 0xFA20_04F4- Reserved 0xFA20_0CFC DBGSTATUS 0xFA20_0D00 Specifies the Debug Status Register. For more information, refer to page 3-37 of “PL330 TRM”.
Page 715 S5PC110_UM 1 DMA CONTROLLER Table 1-3 DMA_peri0 Register Summary Register Address Description Reset Value 0xE090_0000 Specifies the DMA Status Register. For more information, refer to page 3-11 of “PL330 TRM”. 0xE090_0004 Specifies the DMA Program Counter Register. For more information, refer to page 3-13 of “PL330 TRM”.
Page 716 S5PC110_UM 1 DMA CONTROLLER Register Address Description Reset Value 0xE090_0120 Specifies the Channel Status for DMA Channel 4. 0xE090_0128 Specifies the Channel Status for DMA Channel 5. 0xE090_0130 Specifies the Channel Status for DMA Channel 6. 0xE090_0138 Specifies the Channel Status for DMA Channel 7. Channel Program Counter Registers.
Page 717 S5PC110_UM 1 DMA CONTROLLER Register Address Description Reset Value DA_7 0xE090_04E4 Specifies the Destination Address for DMA Channel Channel Control Registers. For more information, refer to page 3-30 of “PL330 TRM”. CC_0 0xE090_0408 Specifies the Channel Control for DMA Channel 0. CC_1 0xE090_0428 Specifies the Channel Control for DMA Channel 1.
Page 718 S5PC110_UM 1 DMA CONTROLLER Register Address Description Reset Value Reserved 0xE090_04B4- Reserved 0xE090_04BC Reserved 0xE090_04D4- Reserved 0xE090_04DC Reserved 0xE090_04F4- Reserved 0xE090_0CFC DBGSTATUS 0xE090_0D00 Specifies the Debug Status Register on page 3-37 of “TRM”. DBGCMD 0xE090_0D04 Specifies the Debug Command Register. For more information, refer to page 3-37 of “PL330 TRM”.
Page 719 S5PC110_UM 1 DMA CONTROLLER Table 1-4 DMA_peri0 Register Summary Register Address Description Reset Value 0xE090_0000 Specifies the DMA Status Register. For more information, refer to page 3-11 of “PL330 TRM”. 0xE090_0004 Specifies the DMA Program Counter Register. For more information, refer to page 3-13 of “PL330 TRM”.
Page 720 S5PC110_UM 1 DMA CONTROLLER Register Address Description Reset Value 0xE090_0120 Specifies the Channel Status for DMA Channel 4. 0xE090_0128 Specifies the Channel Status for DMA Channel 5. 0xE090_0130 Specifies the Channel Status for DMA Channel 6. 0xE090_0138 Specifies the Channel Status for DMA Channel 7. Channel Program Counter Registers.
Page 721 S5PC110_UM 1 DMA CONTROLLER Register Address Description Reset Value DA_7 0xE090_04E4 Specifies the Destination Address for DMA Channel Channel Control Registers. For more information, refer to page 3-30 of “PL330 TRM”. CC_0 0xE090_0408 Specifies the Channel Control for DMA Channel 0. CC_1 0xE090_0428 Specifies the Channel Control for DMA Channel 1.
Page 722 S5PC110_UM 1 DMA CONTROLLER Register Address Description Reset Value Reserved 0xE090_04B4- Reserved 0xE090_04BC Reserved 0xE090_04D4- Reserved 0xE090_04DC Reserved 0xE090_04F4- Reserved 0xE090_0CFC DBGSTATUS 0xE090_0D00 Specifies the Debug Status Register on page 3-37 of “TRM”. DBGCMD 0xE090_0D04 Specifies the Debug Command Register. For more information, refer to page 3-37 of “PL330 TRM”.
Page 723 S5PC110_UM 1 DMA CONTROLLER 1.2.1.1 Channel Control Register for DMA_mem (CC, R) • CC_0, R, Address = 0xFA20_0408 • CC_1, R, Address = 0xFA20_0428 • CC_2, R, Address = 0xFA20_0448 • CC_3, R, Address = 0xFA20_0468 • CC_4, R, Address = 0xFA20_0488 •...
Page 724 S5PC110_UM 1 DMA CONTROLLER 1.2.1.2 Channel Control Register for DMA_PERI(0,1) (CC, R) • CC_0, R, Address = 0xE090_0408, 0xE0A0_0408 • CC_1, R, Address = 0xE090_0428, 0xE0A0_0428 • CC_2, R, Address = 0xE090_0448, 0xE0A0_0448 • CC_3, R, Address = 0xE090_0468, 0xE0A0_0468 •...
Page 725 S5PC110_UM 1 DMA CONTROLLER 1.2.1.3 Configuration Register0 for DMA_PERI(0,1) (CR0, R) • CR0 for DMA_PERI0, R, Address = 0xE090_0E00 • CR0 for DMA_PERI1, R, Address = 0xE0A0_0E00 Description Initial State num_events [21:17] Specifies the number of interrupt outputs that the DMAC 0x1F provides.
Page 726 S5PC110_UM 1 DMA CONTROLLER 1.2.1.4 Configuration Register1 for DMA_PERI(0,1) (CR1, R) • CR1 for DMA_PERI0, R, Address = 0xE090_0E04 • CR1 for DMA_PERI1, R, Address = 0xE0A0_0E04 Description Initial State num_i-cache_lines [7:4] The read value is always 7. It means DMA_PERI(0,1) has 8 i- cache lines.
Page 727 S5PC110_UM 1 DMA CONTROLLER 1.2.1.7 Configuration Register4 for DMA_PERI(0,1) (CR4, R) • CR4 for DMA_PERI0, R, Address = 0xE090_0E10 • CR4 for DMA_PERI1, R, Address = 0xE0A0_0E10 Description Initial State [31:0] Specifies the security state of peripheral request interfaces. 0xFFFF_FFFF Bit [N] = 1: Assigns peripheral request interface N to non- secure state.
Page 728 S5PC110_UM 1 DMA CONTROLLER 1.2.1.9 Configuration Register0 for DMA_mem (CR0, R, Address = 0xFA20_0E00) Description Initial State num_events [21:17] Specifies the number of interrupt outputs that the DMAC 0x1F provides. b11111 = 32 interrupt outputs, irq[31:0] num_periph_req [16:12] Specifies the number of peripheral request interfaces that the DMAC provides.
Page 729 S5PC110_UM 1 DMA CONTROLLER 1.2.1.11 Configuration Register2 for DMA_MEM (CR2, R, Address = 0xFA20_0E08) Description Initial State boot_addr [31:0] Specifies the value of boot_addr[31:0] when DMAC exits from reset. 32’b0 1.2.1.12 Configuration Register3 for DMA_MEM (CR3, R, Address = 0xFA20_0E0C) Description Initial State [31:0]...
Page 730 S5PC110_UM 1 DMA CONTROLLER 1.2.1.14 Configuration Register DN for DMA_MEM (CRdn, R, Address = 0xFA20_0E14) CRDn Description Initial State data_buffer_dep [29:20] Specifies the number of lines that the data buffer contains. 0x1F b000011111 = 32 lines rd_q_dep [19:16] Specifies the depth of read queue. b0111 = 8 lines rd_cap [14:12] Specifies the read issuing capability that programs the number...
Page 731: Instruction
S5PC110_UM 1 DMA CONTROLLER 1.3 INSTRUCTION Table 1-5 Instruction Syntax Summary Thread usage: Mnemonic Instruction Description M = DMA manager C = DMA channel DMAADDH Add Halfword See DMAADDH on page 4-5 of “PL330 TRM”. DMAEND See DMAEND on page 4-5 of “PL330 TRM”. DMAFLUSHP Flush and notify See DMAFLUSHP on page 4-6 of “PL330...
Page 732: Key Instruction
S5PC110_UM 1 DMA CONTROLLER 1.3.1 KEY INSTRUCTION To run the channel thread, you must write assembly code. The description of key instruction is listed below. For full instruction set, refer to Chapter 4, “PL330 TRM”. 1.3.1.1 DMAMOV “Move” instructs the DMAC to move 32-bits immediately into Source Address REG (SAR), Destination Address REG (DAR), and Channel Control REG (CCR).
Page 733 S5PC110_UM 1 DMA CONTROLLER 1.3.1.2 DMALD, DMALDP “Load” instructs the DMAC to perform DMA load using AXI transactions specified by SAR and CCR. For example, if you define CCR as 32-bit and burst length as 2, the DMALD generates a bus transaction of 32-bit and burst length 2.
Page 734: Usage Model
S5PC110_UM 1 DMA CONTROLLER 1.3.2 USAGE MODEL PL330 needs its own binary. The usage model is described as follows: 1. Load DMA binary into memory. 2. Use DMA debug SFRs to start DMA controller, PL330. − A. Using debug SFRs DBGCMD, DBGINST0, and DBGINST1 (all write-only) Before writing the above three SFRs, check whether DBGSTATUS is busy or not.
Page 735 S5PC110_UM 1 DMA CONTROLLER 1.3.2.1 Security Scheme DMA_mem runs in both secure and non-secure modes, while DMA_peri runs only in non-secure mode. 1. Channel thread − A. DMA_mem: Runs in both secure (ns bit at DMAGO instruction is 0) and non-secure (ns bit at DMAGO instruction is 1) modes.
Page 736 S5PC110_UM 1 DMA CONTROLLER 1.3.2.2 Interrupts DMAC provides IRQ signals for use as level sensitive interrupts to external CPUs. If you program the Interrupt Enable Register to generate an interrupt after DMAC executes DMASEV, it sets the corresponding IRQ as high. You can clear the interrupt by writing to the Interrupt Clear Register.
Page 737 Section 7 TIMER...
Page 738 Table of Contents Pulse Width Modulation Timer..............1-1 1.1 Overview of Pulse Width Modulation Timer..................... 1-1 1.2 Key Features of Pulse Width Modulation Timer ..................1-4 1.3 PWM Operation............................1-5 1.3.1 Prescaler and Divider ........................1-5 1.3.2 Basic Timer Operation........................1-5 1.3.3 Auto-reload and Double Buffering ....................
Page 739 4.1 Overview of Real Time Clock........................4-1 4.2 Key Features of Real Time Clock ......................4-1 4.2.1 Real Time Clock Operation Description ................... 4-2 4.3 Leap Year Generator ..........................4-3 4.4 Read / Write Register..........................4-4 4.4.1 Backup Battery Operation ........................ 4-4 4.5 Alarm Function ............................
Page 740 List of Figures Figure Title Page Number Number Figure 1-1 Simple Example of a PWM Cycle ..................... 1-2 Figure 1-2 PWM TIMER Clock Tree Diagram....................1-3 Figure 1-3 Timer Operations ..........................1-5 Figure 1-4 Example of Double Buffering Feature ....................1-7 Figure 1-5 Example of a Timer Operation......................
Page 741 List of Tables Table Title Page Number Number Table 1-1 Minimum and Maximum Resolution based on Prescaler and Clock Divider Values ......1-5 Table 1-1 Tick Interrupt Resolution ........................4-5...
Page 742: Pulse Width Modulation Timer
1.1 OVERVIEW OF PULSE WIDTH MODULATION TIMER The S5PC110 has five 32-bit Pulse Width Modulation (PWM) timers. These timers generate internal interrupts for the ARM subsystem. In addition, Timers 0, 1, 2 and 3 include a PWM function, which drives an external I/O signal.
Page 743 S5PC110_UM 1 PULSE WIDTH MODULATION TIMER shows a simple example of a PWM cycle. Figure 1-1 TOUTn Figure 1-1 Simple Example of a PWM Cycle Steps in PWM cycle: • Initialize the TCNTBn register with 159(50+109) and TCMPBn with 109. •...
Page 744 S5PC110_UM 1 PULSE WIDTH MODULATION TIMER TCMPB0 TCNTB0 PCLK XpwmTOUT0 SCLK_PWM DeadZone Control Generator Logic0 Deadzone 8BIT PRESCALER TCMPB1 TCNTB1 1/16 XpwmTOUT1 Control Logic1 SCLK_PWM SCLK_PWM Deadzone TCMPB2 TCNTB2 SCLK_PWM XpwmTOUT2 Control Logic2 TCMPB3 TCNTB3 SCLK_PWM XpwmTOUT3 Control 8BIT Logic3 PRESCALER 1/16 TCNTB4...
Page 745: Key Features Of Pulse Width Modulation Timer
S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.2 KEY FEATURES OF PULSE WIDTH MODULATION TIMER The Features supported by the PWM include: • Five 32-bit Timers. • Two 8-bit Clock Prescalers providing first level of division for the PCLK, and five Clock Dividers and Multiplexers providing second level of division for the Prescaler clock and SCLK_PWM Programmable Clock Select Logic for individual PWM Channels.
Page 746: Pwm Operation
S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.3 PWM OPERATION 1.3.1 PRESCALER AND DIVIDER An 8-bit prescaler and 3-bit divider generates the following output frequencies: Table 1-1 Minimum and Maximum Resolution based on Prescaler and Clock Divider Values 4-bit Divider Settings Minimum Resolution Maximum Resolution Maximum Interval...
Page 747 S5PC110_UM 1 PULSE WIDTH MODULATION TIMER To generate interrupt at intervals 3cycle of XpwmTOUTn, set TCNTBn, TCMPBn and TCON register as shown in Figure 1-3. Steps to generate interrupt: 1. Set TCNTBn=3 and TCMPBn=1. 2. Set auto-reload=1 and manual update=1. If manual update bit is 1, then TCNTBn and TCMPBn values are loaded to TCNTn and TCMPn.
Page 748: Auto-Reload And Double Buffering
S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.3.3 AUTO-RELOAD AND DOUBLE BUFFERING The PWM Timers includes a double buffering feature, which changes the reload value for the next timer operation without stopping the current timer operation. The timer value is written into TCNTBn (Timer Count Buffer register) and the current counter value of the timer is read from TCNTOn (Timer Count Observation register).
Page 749: Timer Operation Example
S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.3.4 TIMER OPERATION EXAMPLE Example of timer operation is shown in Figure 1-5. TOUTn Figure 1-5 Example of a Timer Operation Steps in timer operation: 1. Enable the auto-reload feature. Set the TCNTBn as 159(50+109) and TCMPBn as 109. Set the manual update bit on and set the manual update bit off.
Page 750: Initialize Timer (Setting Manual-Up Data And Inverter)
S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.3.5 INITIALIZE TIMER (SETTING MANUAL-UP DATA AND INVERTER) User must define the starting value of the TCNTn, because an auto-reload operation of the timer occurs when the down counter reaches to 0. In this case, the starting value must be loaded by manual update bit. The sequence to start a timer is as follows: 1.
Page 751: Output Level Control
S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.3.7 OUTPUT LEVEL CONTROL Inverter off Inverter on Initial State Period 1 Period 2 Timer stop Figure 1-7 Inverter on/off Steps to maintain TOUT as high or low (Assume that inverter is off). 1. Turn off the auto-reload bit. Then, TOUTn goes to high level and the timer is stopped after TCNTn reaches to 0.
Page 752: Dead Zone Generator
S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.3.8 DEAD ZONE GENERATOR This feature inserts the time gap between a turn-off and turn-on of two different switching devices. This time gap prohibits the two switching device turning on simultaneously even for a very short time. TOUT_0 specifies the PWM output.
Page 753: I/O Description
S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.4 I/O DESCRIPTION Signal Description Type TOUT_0 Output PWMTIMER TOUT[0] XpwmTOUT[0] muxed TOUT_1 Output PWMTIMER TOUT[1] XpwmTOUT[1] muxed TOUT_2 Output PWMTIMER TOUT[2] XpwmTOUT[2] muxed TOUT_3 Output PWMTIMER TOUT[3] XpwmTOUT[3] muxed NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals. 1-12...
Page 754: Register Description
S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.5 REGISTER DESCRIPTION 1.5.1 REGISTER MAP Register Address Description Reset Value TCFG0 0xE250_0000 Specifies the Timer Configuration Register 0 that 0x0000_0101 configures the two 8-bit Prescaler and DeadZone Length TCFG1 0xE250_0004 Specifies the Timer Configuration Register 1 that 0x0000_0000 controls 5 MUX Select Bit TCON...
Page 755 S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.5.1.1 Timer Configuration Register (TCFG0, R/W, Address = 0xE250_0000) Timer Input Clock Frequency = PCLK / ( {prescaler value + 1} ) / {divider value} {prescaler value} = 1~255 {divider value} = 1, 2, 4, 8, 16, TCLK Dead zone length = 0~254 TCFG0 Description...
Page 756 S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.5.1.2 Timer Configuration Register (TCFG1, R/W, Address = 0xE250_0004) TCFG1 Description Initial State Reserved [31:24] Reserved Bits 0x00 Divider MUX4 [19:16] Selects Mux input for PWM Timer 4 0x00 0000 = 1/1 0001 = 1/2 0010 = 1/4 0011 = 1/8 0100 = 1/16...
Page 757 S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.5.1.3 Timer Control Register (CON, R/W, Address = 0xE250_0008) TCON Description Initial State Reserved [31:23] Reserved Bits 0x000 Timer 4 Auto Reload on/off [22] 0 = One-Shot 1 = Interval Mode(Auto-Reload) Timer 4 Manual Update [21] 0 = No Operation 1 = Update TCNTB4...
Page 758 S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.5.1.4 Timer0 Counter Register (TCNTB0, R/W, Address = 0xE250_000C) TCNTB0 Description Initial State Timer 0 Count Buffer [31:0] Timer 0 Count Buffer Register 0x0000_0000 1.5.1.5 Timer0 Compare Register (TCMPB0, R/W, Address = 0xE250_0010) TCMPB0 Description Initial State Timer 0 Compare Buffer...
Page 759 S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.5.1.10 Timer2 Counter Register (TCNTB2, R/W, Address = 0xE250_0024) TCNTB2 Description Initial State Timer 2 Count Buffer [31:0] Timer 2 Count Buffer Register 0x0000_0000 1.5.1.11 Timer2 Compare Register (TCMPB2, R/W, Address = 0xE250_0028) TCMPB2 Description Initial State Timer 2 Compare Buffer...
Page 760 S5PC110_UM 1 PULSE WIDTH MODULATION TIMER 1.5.1.16 Timer4 Counter Register (TCNTB4, R/W, Address = 0xE250_003C) TCNTB4 Description Initial State Timer 4 Count Buffer [31:0] Timer 4 Count Buffer Register 0x0000_0000 1.5.1.17 Timer4 Observation Register (TCNTO4, R, Address = 0xE250_0040) TCNTO4 Description Initial State Timer 4 Count Observation...
Page 761: System Timer
S5PC110_UM 2 SYSTEM TIMER SYSTEM TIMER 2.1 OVERVIEW OF SYSTEM TIMER System timer provides two distinctive features, namely: It provides 1ms time tick at any power mode except sleep mode. Changeable interrupt interval without stopping reference tick timer. Figure 2-1 Overall System Timer Block Diagram...
Page 762: Key Features Of System Timer
Two Separate Timers There are two separate system timers in S5PC110. The first timer is used for tick generation, while the other is used for interrupt generation. Two independent SFR sets and logic blocks are used for tick and interrupt region.
Page 763: Detailed Operation
S5PC110_UM 2 SYSTEM TIMER 2.4 DETAILED OPERATION Figure 2-3 Timer Operation with Always on of Auto-reload Usually, the tick interval is fixed after initial setting and you can change the interrupt interval at run-time. Figure 2-3 shows the detailed operation of interrupt counter (INTCNT) and interrupt counter observation SFR (ICNTO) with auto-reload.
Page 764: Tick Generation With Fractional Divider
S5PC110_UM 2 SYSTEM TIMER 2.5 TICK GENERATION WITH FRACTIONAL DIVIDER System timer uses fractional divider to generate tick with any input clock. Especially, system timer can make approximate 1ms tick with RTC input clock (32.768 kHz). The output clock from fractional divider can have local frequency error. If local frequency error is not important for some applications, you can use that output clock with low-power consumption.
Page 765 S5PC110_UM 2 SYSTEM TIMER 2. 1ms with RTC clock Write TCFG[15] as 1 Write TICNTB as 15 and any value to TFCNTB. Then you can get approximate 1ms tick. Although this tick has local error (frequency of one tick is 0.993 kHz or 1.024kHz, they are not 1ms tick), after 125 ticks, it represents exact 125ms passed.
Page 766: Usage Model
S5PC110_UM 2 SYSTEM TIMER 2.6 USAGE MODEL Follow the restrictions given below: • TCLKB must be equal to or slower than PCLK. • Set the count value as high as possible (To improve resolution). • TCFG and tick interval must not be changed at run-time. If you want to change them, stop timers, do TICK SW reset (TCFG[16]) in advance and then change.
Page 767: Start Timer
S5PC110_UM 2 SYSTEM TIMER 2.6.4 START TIMER 1. Reset tick generation logic (by setting TCFG[16] as 1). And TCFG[16] is auto-cleared. 2. Set TCFG SFR to make appropriate TCLK. A. Select clock source. B. Set pre-scaler and divider value. 3. Set tick counter by writing appropriate values to TICNTB and TFCNTB (if you use fractional divider) SFR. 4.
Page 768: I/O Description
S5PC110_UM 2 SYSTEM TIMER 2.7 I/O DESCRIPTION Signal Description Type XT_I & In& XXTI & Dedicated Oscillator pads for system clock XT_O XXTO XT_RTC_I & In& XrtcXTI & Dedicated Oscillator pads for RTC clock XT_RTC_O XrtcXTO XT_USB_I & XusbXTI & Oscillator pads for USB clock Dedicated XT_USB_O...
Page 769: Register Description
S5PC110_UM 2 SYSTEM TIMER 2.8 REGISTER DESCRIPTION 2.8.1 REGISTER MAP Register Address Description Reset Value Software Interface and Registers TCFG E260_0000 Specifies the Configures 8-bit-Prescaler and 0x0000_0000 Clock MUX TCON E260_0004 Specifies the Timer Control Register 0x0000_0000 TICNTB E260_0008 Specifies the Tick Integer Count Buffer Register 0x0000_0000 TICNTO E260_000C...
Page 770 S5PC110_UM 2 SYSTEM TIMER 2.8.1.1 Timer Configuration Register (TCFG, R/W, Address = E260_0000) Timer Input Clock Frequency = TCLKB / ({prescaler value + 1} ) / {divider value} {prescaler value} = 1~255 / {divider value} = 1, 2, 4, 8, 16 TCFG Description Initial State...
Page 771 S5PC110_UM 2 SYSTEM TIMER 2.8.1.2 Timer Control Register (TCON, R/W, Address = E260_0004) TCON Description Initial State Reserved [31:6] Reserved Interrupt Type 0 = One-shot mode 1 = Interval mode(auto-reload) Interrupt Manual Update 0 = No operation 1 = Update ICNTB This bit is auto-cleared.
Page 772 S5PC110_UM 2 SYSTEM TIMER 2.8.1.5 TICK Fractional Counter Register (TFCNTB, R/W, Address = E260_0010) TFCNTB Description Initial State Reserved [31:16] Reserved Tick Fractional Count [15:0] Tick Fractional Count Buffer Register Buffer 2.8.1.6 Interrupt Counter Register (ICNTB, R/W, Address = E260_0018) Real Interrupt Counter Value = ICNTB+1.
Page 773 S5PC110_UM 2 SYSTEM TIMER 2.8.1.8 Interrupt Control and Status Register (INT_CSTAT, R/W, Address = E260_0020) INT_CSTAT Description Initial State Reserved [31:11] Reserved TWIE [10] TCON Write Interrupt Enable 0 = Disable 1 = Enable IWIE ICNTB write Interrupt Enable 0 = Disable 1 = Enable TFWIE TFCNTB write Interrupt Enable...
Page 774: Watchdog Timer
3.1 OVERVIEW OF WATCHDOG TIMER The Watchdog Timer (WDT) in S5PC110 is a timing device that resumes the controller operation after malfunctioning due to noise and system errors. WDT can be used as a normal 16-bit interval timer to request interrupt service.
Page 775: Functional Description Of Watchdog Timer
S5PC110_UM 3 WATCHDOG TIMER 3.3 FUNCTIONAL DESCRIPTION OF WATCHDOG TIMER 3.3.1 WATCHDOG TIMER OPERATION shows the functional block diagram of the watchdog timer. The watchdog timer uses PCLK as its Figure 3-1 source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the resulting frequency is divided again.
Page 776: Consideration Of Debugging Environment
3 WATCHDOG TIMER 3.3.4 CONSIDERATION OF DEBUGGING ENVIRONMENT The watchdog timer must not operate if the S5PC110 is in debug mode using Embedded ICE. The watchdog timer determines from the CPU core signal (DBGACK signal) whether it is currently in the debug mode.
Page 777: Register Description
S5PC110_UM 3 WATCHDOG TIMER 3.4 REGISTER DESCRIPTION 3.4.1 REGISTER MAP Register Address Description Reset Value WTCON 0xE270_0000 Watchdog Timer Control Register 0x00008021 WTDAT 0xE270_0004 Watchdog Timer Data Register 0x00008000 WTCNT 0xE270_0008 Watchdog Timer Count Register 0x00008000 WTCLRINT 0xE270_000C Watchdog Timer Interrupt Clear Register...
Page 778 The WTCON register allows you to enable/ disable the watchdog timer, select the clock signal from four different sources, enable/ disable interrupts, and enable/ disable the watchdog timer output. The Watchdog timer is used to restart the S5PC110 to recover from mal-function; if controller restart is not desired, the Watchdog timer should be disabled.
Page 779 S5PC110_UM 3 WATCHDOG TIMER 3.4.1.2 Watchdog Timer Data Register (WTDAT, R/W, Address = 0xE270_0004) The WTDAT register specifies the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) drives the first time-out. In this case, the value of WTDAT is automatically reloaded into WTCNT.
Page 780: Real Time Clock (Rtc)
S5PC110_UM 4 REAL TIME CLOCK (RTC) REAL TIME CLOCK (RTC) 4.1 OVERVIEW OF REAL TIME CLOCK The Real Time Clock (RTC) unit can operate using the backup battery while the system power is off. Although power is off, backup battery can store the time by Second, Minute, Hour, Day of the week, Day, Month, and Year data.
Page 781 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.2.1 REAL TIME CLOCK OPERATION DESCRIPTION Figure 4-1 Real Time Clock Block Diagram...
Page 782 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.3 LEAP YEAR GENERATOR The leap year generator determines the last day of each month out of 28, 29, 30, or 31. This is calculated based on the data from BCDDAY, BCDMON, and BCDYEAR. This block considers leap year while deciding on the last day of a month.
Page 783 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.4 READ / WRITE REGISTER To write the BCD register in RTC block, set the Bit 0 of the RTCCON register. To display the second, minute, hour, day of the week, day, month, and year, the CPU should read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDAYWEEK, BCDDAY, BCDMON, and BCDYEAR registers, respectively, in the RTC block.
Page 784 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.6 TICK TIME INTERRUPT The RTC tick time is used for interrupt request. The TICNT register contains an interrupt enable bit and count value for the interrupt. If the count value reaches ‘0’ if the tick time interrupt occurs. Then the period of interrupt is as follows: •...
Page 785 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.7 32.768KHZ X-TAL CONNECTION EXAMPLE shows a circuit of the RTC unit oscillation at 32.768kHz. The capacitance 20pF of the load capacitor is Figure 4-2 an example value. It should be adjusted according to the crystal load capacitance. Figure 4-2 Main Oscillator Circuit Example 4.8 RTC START...
Page 786 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.9 I/O DESCRIPTION Signal Description Type XT_RTC_I Input 32.768 kHz RTC Oscillator Clock Input XrtcXTI Dedicated XT_RTC_O Output 32.768 kHz RTC Oscillator Clock Output XrtcXTO Dedicated XRTCCLKO Output 32.768 kHz RTC Clock Output (1.8 ~ 3.3V). XRTCCLKO Dedicated This signal is turned off by default.
Page 787 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.10 REGISTER DESCRIPTION 4.10.1 REGISTER MAP Register Address Description Reset Value INTP 0xE280_0030 Specifies the Interrupt Pending Register 0x00000000 RTCCON 0xE280_0040 Specifies the RTC Control Register 0x00000000 TICCNT 0xE280_0044 Specifies the Tick Time Count Register 0x00000000 RTCALM 0xE280_0050...
Page 788 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.10.1.1 Interrupt Pending Register (INTP, R/W, Address = 0xE280_0030) You can clear specific bits of INTP register by writing 1’s to the bits that you want to clear regardless of RTCEN value. INTP Description Initial State Reserved [31:2]...
Page 789 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.10.1.2 Real Time Clock Control Register (RTCCON, R/W, Address = 0xE280_0040) The RTCCON register consists of 10 bits such as the RTCEN, which controls the read/ write enable of the BCD SEL, CNTSEL, CLKRST, TICCKSEL and TICEN for testing, and CLKOUTEN for RTC clock output control. RTCEN bit controls all interfaces between the CPU and the RTC, therefore it should be set to 1 in an RTC control routine to enable data read/ write after a system reset.
Page 790 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.10.1.3 Tick Time Count Register (TICNT, R/W, Address = 0xE280_0044) TICNT Description Initial State TICK_TIME_C [31:0] 32-bit tick time count value. 32’b0 OUNT This value must not be 0. 4.10.1.4 RTC Alarm Control Register (RTCALM, R/W, Address = 0xE280_0050) The RTCALM register determines the alarm enable and the alarm time.
Page 791 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.10.1.5 Alarm Second Data Register (ALMSEC, R/W, Address = 0xE280_0054) ALMSEC Description Initial State Reserved [31:7] Reserved SECDATA [6:4] BCD value for alarm second. 0 ~ 5 [3:0] 0 ~ 9 0000 4.10.1.6 Alarm Min Data Register (ALMMIN, R/W, Address = 0xE280_0058) ALMMIN Description Initial State...
Page 792 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.10.1.9 ALARM Month Data Register (ALMMON, R/W, Address = 0xE280_0064) ALMMON Description Initial State Reserved [31:5] Reserved MONDATA BCD value for alarm month. 0 ~ 1 [3:0] 0 ~ 9 0000 4.10.1.10 ALARM Year Data Register (ALMYEAR, R/W, Address = 0xE280_0068) ALMYEAR Description Initial State...
Page 793 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.10.1.13 BCD Hour Register (BCDHOUR, R/W, Address = 0xE280_0078) BCDHOUR Description Initial State Reserved [31:6] Reserved HOURDATA [5:4] BCD value for hour. 0 ~ 2 [3:0] 0 ~ 9 4.10.1.14 BCD Day Register (BCDDAY R/W, Address = 0xE280_007C) BCDDAY Description Initial State...
Page 794 S5PC110_UM 4 REAL TIME CLOCK (RTC) 4.10.1.17 BCD Year Register (BCDYEAR, R/W, Address = 0xE280_0088) BCDYEAR Description Initial State Reserved [31:8] Reserved YEARDATA [11:8] BCD value for year. 0 ~ 9 [7:4] 0 ~ 9 [3:0] 0 ~ 9 4.10.1.18 Tick Counter Register (CURTICCNT, R, Address = 0xE280_0090) CURTICCNT Description Initial State...
Page 795 Section 8 CONNECTIVITY/ STORAGE...
Page 796 Table of Contents Universal Asynchronous Receiver and Transmitter .......1-1 1.1 Overview of Universal Asynchronous Receiver and Transmitter ............1-1 1.2 KEY Features of Universal Asynchronous Receiver and Transmitter ............. 1-1 1.3 UART Description ............................ 1-3 1.3.1 Data Transmission..........................1-3 1.3.2 Data Reception ..........................1-3 1.3.3 Auto Flow Control (AFC) ........................
Page 797 4.3.1 Register Map ............................ 4-4 4.3.2 Implemented Specific Registers ....................... 4-6 USB2.0 HS OTG ..................5-1 5.1 Overview of USB2.0 HS OTG........................5-1 5.2 Key Features of USB2.0 HS OTG ......................5-1 5.3 Block Diagram of USB2.0 HS OTG ......................5-2 5.4 Modes of Operation ..........................
Page 798 7.4.5 SD Bus Power Control Sequence ....................7-7 7.4.6 Change Bus Width Sequence ......................7-8 7.4.7 Timeout Setting for DAT Line ......................7-9 7.4.8 SD Transaction Generation ......................7-10 7.4.9 SD Command Issue Sequence ...................... 7-11 7.4.10 Command Complete Sequence ....................7-13 7.4.11 Transaction Control with Data Transfer Using DAT Line .............
Page 799 7.10.27 HOST Controller Version Register ..................... 7-93 Transport Stream Interface ...............8-1 8.1 Overview of Transport Stream Interface....................8-1 8.1.1 Key Features of Transport Stream Interface ..................8-1 8.1.2 Broadcast Mode..........................8-2 8.1.3 Block Diagram of TS Interface......................8-4 8.1.4 I/O Description of TSI ........................8-5 8.1.5 Functional Description ........................
Page 800 List of Figures Figure Title Page Number Number Figure 1-1 Block Diagram of UART........................1-2 Figure 1-2 UART AFC Interface......................... 1-4 Figure 1-3 UART Receives the Five Characters Including Two Errors ............. 1-7 Figure 1-4 IrDA Function Block Diagram ......................1-8 Figure 1-5 Serial I/O Frame Timing Diagram (Normal UART) ................
Page 801 Figure 7-9 Timeout Setting Sequence ......................7-11 Figure 7-10 Command Complete Sequence ..................... 7-14 Figure 7-11 Transaction Control with Data Transfer Using DAT Line Sequence (Not using DMA ) ....7-16 Figure 7-12 Transaction Control with Data Transfer Using DAT Line Sequence (Using DMA) ......7-18 Figure 7-13 Block Diagram of ADMA.........................
Page 802 List of Tables Table Title Page Number Number Table 1-1 Interrupts in Connection with FIFO ....................1-6 Table 6-1 Interrupt Request and Clear Conditions .................... 6-2 Table 6-2 Modem Interface Write Timing (Standard Mode)................6-4 Table 6-3 Modem Interface Read Timing (Standard Mode) ................6-5 Table 6-4 Modem Interface Write Timing (Address Muxed mode) ..............
Page 803: Universal Asynchronous Receiver And Transmitter
TRANSMITTER 1.1 OVERVIEW OF UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER The Universal Asynchronous Receiver and Transmitter (UART) in S5PC110 provide four independent asynchronous, and serial input/output (I/O) ports. All the ports operate in an interrupt-based or a DMA-based mode. The UART generates an interrupt or a DMA request to transfer data to and from the CPU and the UART.
Page 804 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER Peripheral BUS Transmitter Transmit FIFO Register (FIFO mode) Transmit Buffer Register Transmit Holding Register (Non-FIFO mode) Transmit Shifter TXDn Control Buad-rate Clock Source Unit Generator Receiver Receive Shifter RXDn Receive Holding Register (Non-FIFO mode only) Receive Buffer Register Receive FIFO Register (FIFO mode)
Page 805: Uart Description
1.3.3 AUTO FLOW CONTROL (AFC) The UART0 and UART1 in S5PC110 support auto flow control (AFC) using nRTS and nCTS signals. UART2 supports auto flow control if TxD3 and RxD3 are set as nRTS2 and nCTS2 by GPA1CON(GPIO SFR). In this case, it can be connected to external UARTs.
Page 806: Example Of Non Auto-Flow Control (Controlling Nrts And Ncts By Software)
S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER Transmission case in Reception case in UART A UART A UART A UART B UART A UART B nCTS nRTS nRTS nCTS Figure 1-2 UART AFC Interface 1.3.4 EXAMPLE OF NON AUTO-FLOW CONTROL (CONTROLLING NRTS AND NCTS BY SOFTWARE) 1.3.4.1 Rx Operation with FIFO 1.
Page 807: Tx/Rx Fifo Trigger Level And Dma Burst Size In Dma Mode
Tx buffer. It is recommended to fill the Tx buffer first and then enable the Tx interrupt. The interrupt controllers of S5PC110 are of the level-triggered type. You must set the interrupt type as ‘Level’ if you program the UART control registers.
Page 808: Uart Error Status Fifo
S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER Table 1-1 Interrupts in Connection with FIFO Type FIFO Mode Non-FIFO Mode Rx interrupt Generated if Rx FIFO count is greater than or equal Generated by receive holding register to the trigger level of received FIFO. whenever receive buffer becomes full.
Page 809 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER Rx FIFO Error Status FIFO break error parity error frame error URXHn UERSTATn Error Status Generator Unit Figure 1-3 UART Receives the Five Characters Including Two Errors...
Page 810 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.3.8.1 Infra-Red (IR) Mode The S5PC110 UART block supports both infra-red (IR) transmission and reception. It is selected by setting the Infra-red-mode bit in the UART line control register (ULCONn). illustrates how to implement the IR Figure 1-4 mode.
Page 811 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER IR Transmit Frame Data Bits Start Stop Pulse Width = 3/16 Bit Frame Time Figure 1-6 Infra-Red Transmit Mode Frame Timing Diagram IR Receive Frame Data Bits Start Stop Figure 1-7 Infra-Red Receive Mode Frame Timing Diagram...
Page 812: Uart Input Clock Diagram Description
1.4 UART INPUT CLOCK DIAGRAM DESCRIPTION Figure 1-8 Input Clock Diagram for UART S5PC110 provides UART with a variety of clocks. As described in the 1-8, the UART is able to select Figure clocks from PCLK, or SCLK_UART, which is from clock controller. You can also select SCLK_UART from PLLs.
Page 813: I/O Description
S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.5 I/O DESCRIPTION Signal Description Type UART_0_RXD Input Receives Data for UART0 XuRXD[0] muxed UART_0_TXD Output Transmits Data for UART0 XuTXD[0] muxed UART_0_CTSn Input Clears to Send(active low) for UART0 XuCTSn[0] muxed UART_0_RTSn Output Requests to Send(active low) for UART0 XuRTSn[0]...
Page 814: Register Description
S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6 REGISTER DESCRIPTION 1.6.1 REGISTER MAP Register Address Description Reset Value ULCON0 0xE290_0000 Specifies the UART Channel 0 Line Control 0x00000000 Register UCON0 0xE290_0004 Specifies the UART Channel 0 Control Register 0x00000000 UFCON0 0xE290_0008 Specifies the UART Channel 0 FIFO Control 0x00000000...
Page 815 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER Register Address Description Reset Value Register UFSTAT1 0xE290_0418 Specifies the UART Channel 1 FIFO Status 0x00000000 Register UMSTAT1 0xE290_041C Specifies the UART Channel 1 Modem Status 0x00000000 Register UTXH1 0xE290_0420 Specifies the UART Channel 1 Transmit Buffer Register URXH1 0xE290_0424...
Page 816 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER Register Address Description Reset Value Register UINTSP2 0xE290_0834 Specifies the UART Channel 2 Interrupt Source 0x00000000 Pending Register UINTM2 0xE290_0838 Specifies the UART Channel 2 Interrupt Mask 0x00000000 Register ULCON3 0xE290_0C00 Specifies the UART Channel 3 Line Control 0x00000000 Register UCON3...
Page 817 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.1 UART Line Control Register • ULCON0, R/W, Address = 0xE290_0000 • ULCON1, R/W, Address = 0xE290_0400 • ULCON2, R/W, Address = 0xE290_0800 • ULCON3, R/W, Address = 0xE290_0C00 There are four UART line control registers in the UART block, namely, ULCON0, ULCON1, ULCON2, and ULCON3.
Page 818 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.2 UART Control Register • UCON0, R/W, Address = 0xE290_0004 • UCON1, R/W, Address = 0xE290_0404 • UCON2, R/W, Address = 0xE290_0804 • UCON3, R/W, Address = 0xE290_0C04 There are four UART control registers in the UART block, namely, UCON0, UCON1, UCON2 and UCON3. UCONn Description Initial State...
Page 819 1.6.1.12 UART Channel Dividing Slot Register S5PC110 use a level-triggered interrupt controller. Therefore, these bits must be set to 1 for every transfer. If the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO, the Rx interrupt is generated (receive time out).
Page 820 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.3 UART FIFO Control Register • UFCON0, R/W, Address = 0xE290_0008 • UFCON1, R/W, Address = 0xE290_0408 • UFCON2, R/W, Address = 0xE290_0808 • UFCON3, R/W, Address = 0xE290_0C08 There are four UART FIFO control registers in the UART block, namely, UFCON0, UFCON1, UFCON2 and UFCON3.
Page 821 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER UFCONn Description Initial State [Channel 2, 3] 000 = 2 byte 001 = 4 bytes 010 = 6 bytes 011 = 8 bytes 100 = 10 bytes 101 = 12 bytes 110 = 14 bytes 111 = 16 bytes Reserved Tx FIFO Reset...
Page 822 1 = 'L' level (Activate nRTS) NOTE: UART 2 supports AFC function, if nRxD3 and nTxD3 are set as nRTS2 and nCTS2 by GPA1CON. UART 3 does not support AFC function, because the S5PC110 has no nRTS3 and nCTS3. 1-20...
Page 823 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.5 UART Tx/Rx Status Register • UTRSTAT0, R, Address = 0xE290_0010 • UTRSTAT1, R, Address = 0xE290_0410 • UTRSTAT2, R, Address = 0xE290_0810 • UTRSTAT3, R, Address = 0xE290_0C10 There are four UART Tx/Rx status registers in the UART block, namely, UTRSTAT0, UTRSTAT1, UTRSTAT2 and UTRSTAT3.
Page 824 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.6 UART Error Status Register • UERSTAT0, R, Address = 0xE290_0014 • UERSTAT1, R, Address = 0xE290_0414 • UERSTAT2, R, Address = 0xE290_0814 • UERSTAT3, R, Address = 0xE290_0C14 There are four UART Rx error status registers in the UART block, namely, UERSTAT0, UERSTAT1, UERSTAT2 and UERSTAT3.
Page 825 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.7 Uart FIFO Status Register • UFSTAT0, R, Address = 0xE290_0018 • UFSTAT1, R, Address = 0xE290_0418 • UFSTAT2, R, Address = 0xE290_0818 UFSTAT3, R, Address = 0xE290_0C18 There are four UART FIFO status registers in the UART block, namely, UFSTAT0, UFSTAT1, UFSTAT2 and UFSTAT3 UFSTATn Description...
Page 826 Initial State Reserved [31:5] Reserved Delta CTS This bit indicates that the nCTS input to the S5PC110 has changed its state since the last time it was read by CPU. (Refer Figure 1-9) 0 = Has not changed 1 = Has changed...
Page 827 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.9 UART Transmit Buffer Register (Holding Register & FIFO Register) • UTXH0, W, Address = 0xE290_0020 • UTXH1, W, Address = 0xE290_0420 • UTXH2, W, Address = 0xE290_0820 • UTXH3, W, Address = 0xE290_0C20 There are four UART transmit buffer registers in the UART block, namely, UTXH0, UTXH1, UTXH2 and UTXH3.
Page 828 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.11 UART Channel Baud Rate Division Register • UBRDIV0, R/W, Address = 0xE290_0028 • UBRDIV1, R/W, Address = 0xE290_0428 • UBRDIV2, R/W, Address = 0xE290_0828 • UBRDIV3, R/W, Address = 0xE290_0C28 UBRDIV n Description Initial State Reserved...
Page 829 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.12 UART Channel Dividing Slot Register • UDIVSLOT0, R/W, Address = 0xE290_002C • UDIVSLOT1, R/W, Address = 0xE290_042C • UDIVSLOT2, R/W, Address = 0xE290_082C • UDIVSLOT3, R/W, Address = 0xE290_0C2C UDIVSLOT n Description Initial State Reserved [31:16]...
Page 830 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER It is recommended to select UDIVSLOTn as described in the following table: Num of 1’s UDIVSLOTn Num of 1’s UDIVSLOTn 0x0000(0000_0000_0000_0000b) 0x5555(0101_0101_0101_0101b) 0x0080(0000_0000_0000_1000b) 0xD555(1101_0101_0101_0101b) 0x0808(0000_1000_0000_1000b) 0xD5D5(1101_0101_1101_0101b) 0x0888(0000_1000_1000_1000b) 0xDDD5(1101_1101_1101_0101b) 0x2222(0010_0010_0010_0010b) 0xDDDD(1101_1101_1101_1101b) 0x4924(0100_1001_0010_0100b) 0xDFDD(1101_1111_1101_1101b) 0x4A52(0100_1010_0101_0010b) 0xDFDF(1101_1111_1101_1111b) 0x54AA(0101_0100_1010_1010b) 0xFFDF(1111_1111_1101_1111b)
Page 831 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.13 UART Interrupt Pending Register • UINTP0, R/W, Address = 0xE290_0030 • UINTP1, R/W, Address = 0xE290_0430 • UINTP2, R/W, Address = 0xE290_0830 • UINTP3, R/W, Address = 0xE290_0C30 Interrupt pending register contains the information of the interrupts that are generated. UINTPn Description Initial State...
Page 832 S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 1.6.1.15 UART Interrupt Mask Register • UINTM0, R/W, Address = 0xE290_0038 • UINTM1, R/W, Address = 0xE290_0438 • UINTM2, R/W, Address = 0xE290_0838 • UINTM3, R/W, Address = 0xE290_0C38 Interrupt mask register contains the information about which interrupt source is masked. If a specific bit is set to 1, interrupt request signal to the Interrupt Controller is not generated even though corresponding interrupt is generated.
Page 833: Iic-Bus Interface
Serial Clock Line (SCL) is used. Both SDA and SCL lines are bi-directional. In multi-master I C-bus mode, multiple S5PC110 RISC microprocessors receive or transmit serial data to or from slave devices. The master S5PC110 initiates and terminates a data transfer over the I C bus.
Page 834: Key Features Of Iic-Bus Inteface
S5PC110_UM 2 IIC-BUS INTERFACE A d d re s s R e g is te r C o m p a ra to r I2 C -B u s C o n tro l L o g ic S C L I2 C C O N I2 C S T A T P C L K...
Page 835: I I C-Bus Interface Operation
S5PC110_UM 2 IIC-BUS INTERFACE 2.3 I C-BUS INTERFACE OPERATION The S5PC110 I C-bus interface has four operation modes, namely: • Master Transmitter Mode • Master Receive Mode • Slave Transmitter Mode • Slave Receive Mode The functional relationships among these operating modes are described below.
Page 836: Data Transfer Format
S5PC110_UM 2 IIC-BUS INTERFACE 2.3.2 DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. There is no limit to transmit bytes per transfer. The first byte following a Start condition should have the address field. If the I C-bus is operating in Master mode, master transmits the address field.
Page 837: Ack Signal Transmission
S5PC110_UM 2 IIC-BUS INTERFACE 2.3.3 ACK SIGNAL TRANSMISSION To complete a one-byte transfer operation, the receiver sends an ACK bit to the transmitter. The ACK pulse occurs at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master generates clock pulse required to transmit the ACK bit.
Page 838: Read-Write Operation
C-bus interface waits until I2CDS register is read. Before the new data is read out, the SCL line is held low. The line is only released after the data has been read. S5PC110 holds the interrupt to identify the completion of new data reception. After the CPU receives the interrupt request, it reads the data from the I2CDS register.
Page 839: Flowcharts Of Operations In Each Mode
S5PC110_UM 2 IIC-BUS INTERFACE 2.3.8 FLOWCHARTS OF OPERATIONS IN EACH MODE Following steps must be executed before any I C Tx/Rx operations: 1. If required, write own slave address on I2CADD register. 2. Set I2CCON register. a) Enable interrupt b) Define SCL period 3.
Page 840 S5PC110_UM 2 IIC-BUS INTERFACE START Master Rx mode has been configured. Write slave address to I2CDS. Write 0xB0 (M/R Start) to I2CSTAT. The data of the I2CDS (slave address) is transmitted. After ACK period interrupt is pending. Stop? Read a new data from Write 0x90 (M/R Stop) I2CDS.
Page 841 S5PC110_UM 2 IIC-BUS INTERFACE START Slave Tx mode has been configured. I2C detects start signal. and, I2CDS receives data. I2C compares I2CADD and I2CDS (the received slave address). Matched? The I2C address match interrupt is generated. Write data to I2CDS. Clear pending bit to resume.
Page 842 S5PC110_UM 2 IIC-BUS INTERFACE START Slave Rx mode has been configured. I2C detects start signal. and, I2CDS receives data. I2C compares I2CADD and I2CDS (the received slave address). Matched? The I2C address match interrupt is generated. Read data from I2CDS. Clear pending bit to resume.
Page 843: I/O Description
S5PC110_UM 2 IIC-BUS INTERFACE 2.4 I/O DESCRIPTION Signal Description Type I2C0_SCL Input/Output I Xi2c0SCL muxed C-Bus Interface0 Serial Clock Line I2C0_SDA Input/Output I Xi2c0SDA muxed C-Bus Interface0 Serial Data Line I2C2_SCL Input/Output I Xi2c2SCL muxed C-BUS Interface2 Serial Clock Line I2C2_SDA Input/Output I Xi2c2SDA...
Page 844: Register Description
S5PC110_UM 2 IIC-BUS INTERFACE 2.5 REGISTER DESCRIPTION 2.5.1 REGISTER MAP Register Address Description Reset Value I2CCON0 0xE180_0000 0x0X Specifies the I C-Bus Interface0 control register I2CSTAT0 0xE180_0004 0x00 Specifies the I C-Bus Interface0 control/status register I2CADD0 0xE180_0008 0xXX Specifies the I C-Bus Interface0address register I2CDS0 0xE180_000C...
Page 845 S5PC110_UM 2 IIC-BUS INTERFACE 2.5.1.1 Multi-Master I C-Bus Control Register • I2CCON0, R/W, Address = 0xE180_0000 • I2CCON2, R/W, Address = 0xE1A0_0000 • I2CCON_HDMI_DDC, R/W, Address = 0xFAB0_0000 • I2CCON_HDMI_PHY, R/W, Address = 0xFA90_0000 I2CCON Description Initial State Acknowledge generation C-bus acknowledge enable bit.
Page 846 S5PC110_UM 2 IIC-BUS INTERFACE 2.5.1.2 Multi-Master I C-Bus Control/Status Register • I2CSTAT0, R/W, Address = 0xE180_0004 • I2CSTAT2, R/W, Address = 0xE1A0_0004 • I2CSTAT_HDMI_DDC, R/W, Address = 0xFAB0_0004 • I2CSTAT_HDMI_PHY, R/W, Address = 0xFA90_0004 I2CSTAT Description Initial State Mode selection [7:6] C-bus master/ slave Tx/Rx mode select bits.
Page 847 S5PC110_UM 2 IIC-BUS INTERFACE 2.5.1.3 Multi-Master I C-Bus Address Register • I2CADD0, R/W, Address = 0xE180_0008 • I2CADD2, R/W, Address = 0xE1A0_0008 • I2CADD_HDMI_DDC, R/W, Address = 0xFAB0_0008 • I2CADD_HDMI_PHY, R/W, Address = 0xFA90_0008 I2CADD Description Initial State Slave address [7:0] Undefined 7-bit slave address, latched from the I...
Page 848 S5PC110_UM 2 IIC-BUS INTERFACE 2.5.1.5 MULTI-MASTER I C-Bus Line Control Register • I2CLC0, R/W, Address = 0xE180_0010 • I2CLC2, R/W, Address = 0xE1A0_0010 • I2CLC_HDMI_DDC, R/W, Address = 0xFAB0_0010 • I2CLC_HDMI_PHY, R/W, Address = 0xFA90_0010 I2CLC Description Initial State Filter enable C-bus filter enable bit.
Page 849: Serial Peripheral Interface
3.1 OVERVIEW OF SERIAL PERIPHERAL INTERFACE The Serial Peripheral Interface (SPI) in S5PC110 transfers serial data using various peripherals. SPI includes two 8, 16, 32-bit shift registers to transmit and receive data. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially).
Page 850: Operation Of Serial Peripheral Interface
3.2.1 OPERATION OF SERIAL PERIPHERAL INTERFACE The SPI transfers 1-bit serial data between S5PC110 and external device. The SPI in S5PC110 supports the CPU or DMA to transmit or receive FIFOs separately and to transfer data in both directions simultaneously. SPI has two channels, TX channel and RX channel.
Page 851 SPICLK. If SPI runs at high operating frequency such as 50MHz, it is difficult to capture the MISO input because the required arrival time of MISO, which is an half cycle period in S5PC110, is shorter than the arrival time of MISO that consists of SPICLK output delay of SPI master, MISO output delay of SPI slave, and MISO input delay of SPI master.
Page 852 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.2.1.8 SPI Transfer Format The S5PC110 supports four different formats for data transfer. describes four waveforms for SPICLK. Figure 3-1 CPOL = 0, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO *MSB *MSB : MSB of previous frame...
Page 853: Io Description
S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.3 IO DESCRIPTION The following table lists the external signals between the SPI and external device. The unused SPI ports are used as General Purpose I/O ports. Refer to “General Purpose I/O” chapter for more information. Signal Description Type...
Page 854: Register Description
S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4 REGISTER DESCRIPTION 3.4.1 REGISTER MAP Register Address Description Reset Value CH_CFG0 0xE1300000 Specifies the SPI Port 0 Configuration Register CLK_CFG0 0xE1300004 Specifies the SPI Port 0 Clock Configuration Register MODE_CFG0 0xE1300008 Specifies the SPI Port 0 FIFO Control Register CS_REG0 0xE130000C...
Page 855 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE Register Address Description Reset Value SWAP_CFG1 0xE1400028 Specifies the SPI Port 1 Swap Config Register FB_CLK_SEL1 0xE140002C Specifies the SPI Port 1 Feedback Clock Selection Register...
Page 856 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.1.1 Setting Sequence of Special Function Register Steps to set Special Function Register (nCS manual mode): 1. Set Transfer Type. (CPOL & CPHA set) 2. Set Feedback Clock Selection register. 3. Set Clock configuration register. 4.
Page 857: Special Function Register
S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.2 SPECIAL FUNCTION REGISTER 3.4.2.1 SPI Configuration Register • CH_CFG0, R/W, Address = 0xE130_0000 • CH_CFG1, R/W, Address = 0xE140_0000 CH_CFGn Description Initial State HIGH_SPEED_EN Slave TX output time control bit. If this bit is enabled, slave TX output time is reduced as much as half period of SPICLKout period.
Page 858 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.2.2 Clock Configuration Register • CLK_CFG0, R/W, Address = 0xE130_0004 • CLK_CFG1, R/W, Address = 0xE140_0004 CLK_CFGn Description Initial State SPI_CLKSEL Clock source selection to generate SPI clock-out 0 = PCLK 1 = SPI_EXT_CLK ENCLK Clock enable/ disable 0 = Disable 1 = Enable...
Page 859 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.2.3 SPI FIFO Control Register • MODE_CFG0, R/W, Address = 0xE130_0008 • MODE_CFG1, R/W, Address = 0xE140_0008 MODE_CFGn Description Initial State CH_WIDTH [30:29] 00 = Byte 01 = Halfword 10 = Word 11 = Reserved TRAILING_CNT [28:19] Count value from writing the last data in RX FIFO to flush trailing bytes in FIFO...
Page 860 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.2.4 Slave Selection Signal Control Signal • CS_REG0, R/W, Address = 0xE130_000C • CS_REG1, R/W, Address = 0xE140_000C CS_REGn Description Initial State NCS_TIME_COUNT [9:4] NSSOUT inactive time = ((nCS_time_count+3)/2) x SPICLKout Reserved [3:2] Reserved AUTO_N_MANUAL Chip select toggle manual or auto selection 0 = Manual 1 = Auto...
Page 861 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.2.5 SPI Interrupt Enable Register • SPI_INT_EN0, R/W, Address = 0xE130_0010 • SPI_INT_EN1, R/W, Address = 0xE140_0010 SPI_INT_ENn Description Initial State INT_EN_TRAILING Interrupt Enable for trailing count to be 0 0 = Disables 1 = Enables INT_EN_RX_OVERRUN Interrupt Enable for RxOverrun 0 = Disables...
Page 862 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.2.6 SPI Status Register • SPI_STATUS0, R, Address = 0xE130_0014 • SPI_STATUS1, R, Address = 0xE140_0014 SPI_STATUSn Description Initial State TX_DONE [25] Indication of transfer done in Shift register(master mode only) 0 = All case except blow case 1 = If Tx FIFO and shift register are empty TRAILING_BYTE [24]...
Page 863 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.2.7 SPI TX Data Register • SPI_TX_DATA, W, Address = 0xE130_0018 • SPI_TX_DATA, W, Address = 0xE140_0018 SPI_TX_DATAn Description Initial State TX_DATA [31:0] This field contains the data to be transmitted over the SPI channel. 3.4.2.8 SPI RX Data Register •...
Page 864 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.2.10 Status Pending Clear Register • PENDING_CLR_REG0, R/W, Address = 0xE130_0024 • PENDING_CLR_REG1, R/W, Address = 0xE140_0024 PENDING_CLR_REGn Description Initial State TX_UNDERRUN_CLR TX underrun pending clear bit 0 = Non-Clear 1 = Clear TX_OVERRUN_CLR TX overrun pending clear bit 0 = Non-Clear 1 = Clear RX_UNDERRUN_CLR...
Page 865 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.2.11 SWAP Config Register • SWAP_CFG_REG0, R/W, Address = 0xE130_0028 • SWAP_CFG_REG1, R/W, Address = 0xE140_0028 SWAP_CFGn Description Initial State RX_HWORD_SWAP 0 = Off 1 = Swap RX_BYTE_SWAP 0 = Off 1 = Swap RX_BIT_SWAP 0 = Off 1 = Swap RX_SWAP_EN...
Page 866 S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE 3.4.2.12 FeedBack Clock Selection Register • FB_CLK_SEL_REG0, R/W, Address = 0xE130_002C • FB_CLK_SEL_REG1, R/W, Address = 0xE140_002C FB_CLK_SELn Description Initial State FB_CLK_SEL [1:0] In master mode, SPI uses a clock which is feedback from the SPICLK.
Page 867: Usb 2.0 Host Controller
USB 2.0 HOST CONTROLLER 4.1 OVERVIEW OF USB 2.0 HOST CONTROLLER S5PC110 supports a single port USB host interface. The key features of this interface include: • Complies with Enhanced HCI (EHCI) Rev 1.0a and Open HCI (OHCI) Rev1.0 specifications (Both EHCI and OHCI compatible).
Page 868: Block Diagram Of Usb System And Usb 2.0 Host Controller
S5PC110_UM 4 USB 2.0 HOST CONTROLLER 4.2 BLOCK DIAGRAM OF USB SYSTEM AND USB 2.0 HOST CONTROLLER USB HOST 2.0 controller is composed of two independent blocks, namely, USB HOST 2.0 controller and USB PHY Controller. Each of these blocks has an AHB Slave interface that provides the microcontroller with read and write access to the Control and Status Registers (CSRs).
Page 869 S5PC110_UM 4 USB 2.0 HOST CONTROLLER USB 2.0 Host Controller USB 2.0 EHCI Host Controller EHCI Generation Operation Register XuhostDP XuhostDM PHY1 Root Hub Master/Slave List Porcessor Interfac Packet Buffer USB 1.1 OHCI Host Controller Figure 4-2 USB 2.0 Host Controller Block Diagram...
Page 870: Register Description
S5PC110_UM 4 USB 2.0 HOST CONTROLLER 4.3 REGISTER DESCRIPTION 4.3.1 REGISTER MAP The USB host controller in S5PC110X complies with both EHCI Rev 1.0a and OHCI Rev 1.0 specification. For more information, Refer to EHCI 1.0a and OHCI 1.0 specification. Register Address Description...
Page 871 S5PC110_UM 4 USB 2.0 HOST CONTROLLER Register Address Description Reset Value HcControl 0xEC30_0004 Specifies the USB Host Controller Control 0x0000_0000 Register. HcCommonStatus 0xEC30_0008 Specifies the USB Host Controller 0x0000_0000 Command Status Register. HcInterruptStatus 0xEC30_000C Specifies the USB Host Controller 0x0000_0000 Interrupt Status Register.
Page 872 S5PC110_UM 4 USB 2.0 HOST CONTROLLER 4.3.2 IMPLEMENTED SPECIFIC REGISTERS Specific registers allow you to program configurable registers such as the Packet Buffer Depth, Break Memory Transfer, Frame Length, and UTMI Control and Status Registers Access. 4.3.2.1 Programmable Microframe Base Value (INSNREG00, R/W, Address = 0xEC20_0090) INSNREG00 Description Initial State...
Page 873 S5PC110_UM 4 USB 2.0 HOST CONTROLLER INSNREG00 Description Initial State Writing 1’b1 enables the microframe length value field of this register. 4.3.2.2 Programmable Packet Buffer OUT/IN Thresholds (INSNREG01, R/W, Address = 0xEC20_0094) INSNREG01 Description Initial State [31:0] [31:16] OUT Threshold 0x00400040 [15:0] IN Threshold Specifies the number of DWORDs (32-bit entries).
Page 874 S5PC110_UM 4 USB 2.0 HOST CONTROLLER 4.3.2.3 Programmable Packet Buffer Depth (INSNREG02, R/W, Address = 0xEC20_0098) INSNREG02 Description Initial State [31:0] Specifies the number of DWORDs (32-bit entries). 0x00000100 4.3.2.4 Break Memory Transfer (INSNREG03, R/W, Address = 0xEC20_009C) INSNREG03 Description Initial State Reserved [31:13] -...
Page 875 S5PC110_UM 4 USB 2.0 HOST CONTROLLER 4.3.2.5 Used for Debug Only (INSNREG04, R/W, Address = 0xEC20_00A0) INSNREG04 Description Initial State Reserved [31:6] 0x00000000 Used only for debug purposes. 1'b0 = by default, the automatic feature is enabled. The • Suspend signal is deasserted when run/stop is reset by software, but the hchalted bit is not yet set.
Page 876 S5PC110_UM 4 USB 2.0 HOST CONTROLLER 4.3.2.6 UTMI Configuration (INSNREG05, R/W, Address = 0xEC20_00A4) INSNREG05 Description Initial State Reserved [31:18] - 0x00001000 [17] Specifies VBusy (Software RO). The hardware indicates that a write to this register has occurred and the hardware is processing the operation defined by the data written.
Page 877 USB2.0 HS OTG 5.1 OVERVIEW OF USB2.0 HS OTG Samsung USB On-The-Go (OTG) is a Dual-Role Device (DRD) controller, which supports both device and host functions. It is fully compliant with the On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a. It supports high-speed (HS, 480-Mbps), full-speed (FS, 12-Mbps), and low-speed (LS, 1.5-Mbps, Host only)
Page 878 S5PC110_UM 5 USB2.0 HS OTG 5.3 BLOCK DIAGRAM OF USB2.0 HS OTG Figure 5-1 System Level Block Diagram USB HS OTG controller is composed of two independent blocks, namely, USB 2.0 OTG and USB PHY Controller. Each of these blocks has an AHB Slave interface that provides the microcontroller with read and write access to the Control and Status Registers (CSRs).
Page 879: Modes Of Operation
S5PC110_UM 5 USB2.0 HS OTG 5.4 MODES OF OPERATION The end user application operates the Link in either DMA or Slave mode. It cannot operate the USB OTG controller using DMA and Slave modes simultaneously. 5.4.1 DMA MODE USB OTG host uses the AHB Master interface to transmit packet data to be fetched (AHB to USB) and receive data update (USB to AHB).
Page 880 S5PC110_UM 5 USB2.0 HS OTG 5.5 POWER MANAGEMENT UNIT SETTING A register in Power Management Unit has to be set for USB to work appropriately. For more information, refer to Power Management Unit. USB_CONTROL Description Initial State ENABLE 1 Enables USB PHY1 1'b0 0 = Disables 1 = Enables...
Page 881 S5PC110_UM 5 USB2.0 HS OTG 5.6 REGISTER MAP 5.6.1 OVERVIEW OF REGISTER MAP To control and observe the OTG PHY, access the USB PHY control registers based on the address EC10_0000h. The OTG Link Core registers is based on the address EC00_0000h, which is classified as follows: •...
Page 882 S5PC110_UM 5 USB2.0 HS OTG 5.6.2 OTG LINK CSR MEMORY MAP shows the OTG link CSR address map. Host and Device mode registers occupy different addresses. Figure 5-2 All registers are implemented in the AHB Clock domain. OTG LINK BASE + 000h Core Global CSRs OTG LINK BASE + 0400h Host Mode CSRs...
Page 883 S5PC110_UM 5 USB2.0 HS OTG 5.6.3 OTG FIFO ADDRESS MAPPING Figure 5-3 OTG FIFO Mapping...
Page 884 S5PC110_UM 5 USB2.0 HS OTG shows the OTG FIFO Address Mapping. The following registers must be programmed as follows; Figure 5-3 In Host Mode • RXFSIZ[31:16] = OTG_RX_DFIFO_DEPTH • NPTXFSIZ[15:0] = OTG_RX_DFIFO_DEPTH • NPTXFSIZ[31:16] = OTG_TX_HNPERIO_DFIFO_DEPTH • HPTXFSIZ[15:0] = OTG_RX_DFIFO_DEPTH + OTG_TX_HNPERIO_DFIFO_DEPTH •...
Page 885 S5PC110_UM 5 USB2.0 HS OTG 5.6.4 APPLICATION ACCESS TO THE CSRS The Access column of each register description that follows specifies how the application and the core access the register fields of the CSRs. The following conventions are used. Read Only The application has permission to read the Register field.
Page 886 S5PC110_UM 5 USB2.0 HS OTG 5.7 I/O DESCRIPTION Signal Description Type XuotgDP Input/ Output Data Plus Signal from the USB Cable XuotgDP Dedicated XuotgDM Input/ Output Data Minus Signal from the USB Cable XuotgDM Dedicated XusbXTI Input Crystal Oscillator XI XusbXTI Dedicated XusbXTO...
Page 887 S5PC110_UM 5 USB2.0 HS OTG 5.8 REGISTER DESCRIPTION 5.8.1 REGISTER MAP Table 5-1 Register Summary of HS USB PHY Controller Register Address Description Reset Value USB PHY Control Registers UPHYPWR 0xEC10_0000 R/W Specifies the USB PHY Power Control Register 0x0000_01F9 UPHYCLK 0xEC10_0004 R/W Specifies the USB PHY Clock Control Register...
Page 888 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value Size Register DIEPTXF7 0xEC00_011C R/W Specifies the Device IN Endpoint Transmit FIFO-7 0x0300_3400 Size Register DIEPTXF8 0xEC00_0120 R/W Specifies the Device IN Endpoint Transmit FIFO-8 0x0300_3700 Size Register DIEPTXF9 0xEC00_0124 R/W Specifies the Device IN Endpoint Transmit FIFO-9 0x0300_3A00 Size Register...
Page 889 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value Register HCCHAR1 0xEC00_0520 R/W Specifies the Host Channel 1 Characteristics 0x0000_0000 Register HCSPLT1 0xEC00_0524 R/W Specifies the Host Channel 1 Spilt Control Register 0x0000_0000 HCINT1 0xEC00_0528 R/W Specifies the Host Channel 1 Interrupt Register 0x0000_0000 HCINTMSK1 0xEC00_052C...
Page 890 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value HCCHAR5 0xEC00_05A0 R/W Specifies the Host Channel 5 Characteristics 0x0000_0000 Register HCSPLT5 0xEC00_05A4 R/W Specifies the Host Channel 5 Spilt Control Register 0x0000_0000 HCINT5 0xEC00_05A8 R/W Specifies the Host Channel 5 Interrupt Register 0x0000_0000 HCINTMSK5 0xEC00_05AC...
Page 891 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value Register HCSPLT9 0xEC00_0624 R/W Specifies the Host Channel 9 Spilt Control Register 0x0000_0000 HCINT9 0xEC00_0628 R/W Specifies the Host Channel 9 Interrupt Register 0x0000_0000 HCINTMSK9 0xEC00_062C R/W Specifies the Host Channel 9 Interrupt Mask 0x0000_0000 Register HCTSIZ9...
Page 892 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value HCCHAR13 0xEC00_06A0 R/W Specifies the Host Channel 13 Characteristics 0x0000_0000 Register HCSPLT13 0xEC00_06A4 R/W Specifies the Host Channel 13 Spilt Control 0x0000_0000 Register HCINT13 0xEC00_06A8 R/W Specifies the Host Channel 13 Interrupt Register 0x0000_0000 HCINTMSK13 0xEC00_06AC...
Page 893 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value DAINT 0xEC00_0818 Specifies the Device ALL Endpoints Interrupt 0x0000_0000 Register DAINTMSK 0xEC00_081C R/W Specifies the Device ALL Endpoints Interrupt Mask 0x0000_0000 Register DVBUSDIS 0xEC00_0828 R/W Specifies the Device VBUS Discharge Time 0x0000_0B8F Register DVBUSPULSE...
Page 894 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value Register DTXFSTS2 0xEC00_0958 Specifies the Device IN Endpoint Transmit FIFO 0x0000_0100 Status Register DIEPDMAB2 0xEC00_095C Specifies the Device IN Endpoint 2 DMA Buffer 0x0000_0000 Address Register DIEPCTL3 0xEC00_0960 R/W Specifies the Device Control IN Endpoint 3 Control 0x0000_0000 Register DIEPINT3...
Page 895 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value Register DIEPINT6 0xEC00_09C8 R/W Specifies the Device IN Endpoint 6 Interrupt 0x0000_0080 Register DIEPTSIZ6 0xEC00_09D0 R/W Specifies the Device IN Endpoint 6 Transfer Size 0x0000_0000 Register DIEPDMA6 0xEC00_09D4 R/W Specifies the Device IN Endpoint 6 DMA Address 0x0000_0000 Register DTXFSTS6...
Page 896 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value Register DTXFSTS9 0xEC00_0A38 Specifies the Device IN Endpoint Transmit FIFO 0x0000_0100 Status Register DIEPDMAB9 0xEC00_0A3C Specifies the Device IN Endpoint 9 DMA Buffer 0x0000_0000 Address Register DIEPCTL10 0xEC00_0A40 R/W Specifies the Device Control IN Endpoint 10 Control 0x0000_0000 Register DIEPINT10...
Page 897 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value Register DIEPINT13 0xEC00_0AA8 R/W Specifies the Device IN Endpoint 13 Interrupt 0x0000_0080 Register DIEPTSIZ13 0xEC00_0AB0 R/W Specifies the Device IN Endpoint 13 Transfer Size 0x0000_0000 Register DIEPDMA13 0xEC00_0AB4 R/W Specifies the Device IN Endpoint 13 DMA Address 0x0000_0000 Register DTXFSTS13...
Page 898 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value DOEPDMA0 0xEC00_0B14 R/W Specifies the Device OUT Endpoint 0 DMA Address 0x0000_0000 Register DOEPDMAB0 0xEC00_0B1C Specifies the Device OUT Endpoint 0 DMA Buffer 0x0000_0000 Address Register DOEPCTL1 0xEC00_0B20 R/W Specifies the Device Control OUT Endpoint 1 0x0000_0000 Control Register DOEPINT1...
Page 899 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value DOEPDMAB4 DOEPDMAB4 Specifies the Device OUT Endpoint 4 DMA Buffer 0x0000_0000 Address Register DOEPCTL5 0xEC00_0BA0 R/W Specifies the Device Control OUT Endpoint 5 0x0000_0000 Control Register DOEPINT5 0xEC00_0BA8 R/W Specifies the Device OUT Endpoint 5 Interrupt 0x0000_0000 Register DOEPTSIZ5...
Page 900 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value DOEPCTL9 0xEC00_0C20 R/W Specifies the Device Control OUT Endpoint 9 0x0000_0000 Control Register DOEPINT9 0xEC00_0C28 R/W Specifies the Device OUT Endpoint 9 Interrupt 0x0000_0000 Register DOEPTSIZ9 0xEC00_0C30 R/W Specifies the Device OUT Endpoint 9 Transfer Size 0x0000_0000 Register DOEPDMA9...
Page 901 S5PC110_UM 5 USB2.0 HS OTG Register Address Description Reset Value DOEPINT13 0xEC00_0CA8 R/W Specifies the Device OUT Endpoint 13 Interrupt 0x0000_0000 Register DOEPTSIZ13 0xEC00_0CB0 R/W Specifies the Device OUT Endpoint 13 Transfer 0x0000_0000 Size Register DOEPDMA13 0xEC00_0CB4 R/W Specifies the Device OUT Endpoint 13 DMA 0x0000_0000 Address Register DOEPDMAB13...
Page 902 S5PC110_UM 5 USB2.0 HS OTG 5.8.2 USB PHY CONTROL REGISTERS 5.8.2.1 USB PHY Power Control Register (UPHYPWR, R/W, Address = 0xEC10_0000) UPHYPWR Description Initial State Reserved [31:9] 23’b0 Reserved Reserved, but should be 0x1 1'b1 Analog USBPHY1, Analog block power down 1'b1 _powerdown1 1'b0: Analog block power up (Normal Operation)
Page 903 S5PC110_UM 5 USB2.0 HS OTG 5.8.2.2 USB PHY Clock Control Register (UPHYCLK, R/W, Address = 0xEC10_0004) UPHYCLK Description Initial State Reserved [31:7] - 25'h0 USBPHY1, Force XO, Bias, Bandgap, and PLL to Remain 1'b0 common_on_n1 Powered During a Suspend This bit controls the power-down signals of sub-blocks in the Common block if the USB PHY1 is suspended.
Page 904 S5PC110_UM 5 USB2.0 HS OTG Figure 5-4 USB PHY Clock Path 5.8.2.3 USB Reset Control Register (URSTCON, R/W, Address = 0xEC10_0008) URSTCON Description Initial State Reserved [31:5] 29'h0 host_sw_rst USB Host LINK S/W Reset 1'b0 phy_sw_rst1 USB PHY1, USB Host LINK S/W Reset 1'b1 The phy1_sw_rst signal must by asserted for at least 10us phylnk_sw_rst...
Page 905 S5PC110_UM 5 USB2.0 HS OTG 5.8.2.4 PHY Tune Register (PHY_TUNE, R/W, Address = 0xEC10_0020, 0xEC10_0024) Caution: USB PHY1:0XEC10_0020, USB PHY0: 0XEC10_0024 UPHYTUNE0, 1 Description Initial State Reserved [31:21] - 11'h0 Reserved [20:17] Reserved, but should be 4’b0100 4'b0100 Otgtune [16:14] VBUS Valid Threshold Adjustment. This bit adjusts the 3'b100 voltage level for the VBUS Valid threshold in USBPHY-n.
Page 906 S5PC110_UM 5 USB2.0 HS OTG 5.8.3 OTG LINK CORE REGISTERS (OTG GLOBAL REGISTERS) These registers are available in both Host and Device modes, and not required to be reprogrammed to switch between these modes. 5.8.3.1 OTG Control and Status Register (GOTGCTL, R/W, Address = 0xEC00_0000) The OTG Control and Status register controls the behavior and reflects the status of the core's OTG function.
Page 907 S5PC110_UM 5 USB2.0 HS OTG GOTGCTL Description Initial State HstNegScs Host Negotiation Success 1'b0 The core sets this bit if host negotiation is successful. The core clears this bit if the HNP Request (HNPReq) bit in this register is set. 1'b0: Host negotiation failure •...
Page 908 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.2 OTG Interrupt Register (GOTGINT, R/W, Address = 0xEC00_0004) The application reads this register at the time of OTG interrupt. To clear the OTG interrupt, application clears the bits in this register. GOTGINT Description Initial State Reserved [31:20] - 12'h0...
Page 909 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.3 OTG AHB Configuration Register (GAHBCFG, R/W, Address = 0xEC00_0008) This register configures the core after power-on or a change in mode of operation. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
Page 910 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.4 OTG USB Configuration Register (GUSBCFG, R/W, Address = 0xEC00_000C) This register configures the core after power-on or a changing to Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB.
Page 911 S5PC110_UM 5 USB2.0 HS OTG GUSBCFG Description Initial State PHYIf PHY Interface 1'b1 The application uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface. Only 16-bit interface is supported. This bit must be set to 1. 1'b0: 8 bits •...
Page 912 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.5 Core Reset Register (GRSTCTL, R/W, Address = 0xEC00_0010) The application uses this register to reset various hardware features inside the core. GRSTCTL Description Initial State AHBIdle [31] AHB Master Idle 1'b1 Indicates that the AHB Master State Machine is in the IDLE condition.
Page 913 S5PC110_UM 5 USB2.0 HS OTG GRSTCTL Description Initial State HSftRst HClk Soft Reset R_WS 1'b0 The application uses this bit to flush the control logic in the AHB Clock domain. Only AHB Clock Domain pipelines are reset. FIFOs are not flushed with this bit. •...
Page 914 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.6 Core Interrupt Register (GINTSTS, R/W, Address = 0xEC00_0014) This register interrupts the application for system-level events in the current mode of operation (Device mode or Host mode). GINTSTS Description Initial State WkUpInt [31] Resume/ Remote Wakeup Detected Interrupt R_SS 1'b0 In Device mode, this interrupt is asserted if a resume is detected...
Page 915 S5PC110_UM 5 USB2.0 HS OTG GINTSTS Description Initial State PrtInt [24] Host Port Interrupt 1'b0 The core sets this bit to indicate a change in port status of one of the OTG core ports in Host mode. The application must read the Host Port Control and Status (HPRT) register to determine the exact event that caused this interrupt.
Page 916 S5PC110_UM 5 USB2.0 HS OTG GINTSTS Description Initial State Incompl [20] Incomplete Isochronous IN Transfer (incompISOIN) R_SS 1'b0 SOIN The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current microframe.
Page 917 S5PC110_UM 5 USB2.0 HS OTG GINTSTS Description Initial State USBSusp [11] USB Suspend R_SS 1'b0 The core sets this bit to indicate that a suspend state was detected on the USB. The core enters the Suspended state if there is no activity on the line_state signal for an extended period of time.
Page 918 S5PC110_UM 5 USB2.0 HS OTG GINTSTS Description Initial State OTGInt OTG Interrupt 1'b0 The core sets this bit to indicate an OTG protocol event. The application must read the OTG Interrupt Status (GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the GOTGINT register to clear this bit.
Page 919 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.7 Core Interrupt Mask Register (GINTMSK, R/W, Address = 0xEC00_0018) This register works with the Core Interrupt register to interrupt the application. If an interrupt bit is masked, the interrupt associated with that bit will not be generated. However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set.
Page 920 S5PC110_UM 5 USB2.0 HS OTG GINTMSK Description Initial State OTGIntMsk OTG Interrupt Mask 1'b0 ModeMisMsk Mode Mismatch Interrupt Mask 1'b0 Reserved 1'b0 5.8.3.8 Receive Status Debug Read/Status Read and Pop Registers (GRXSTSR/GRXSTSP) A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. A read to the Receive Status Read and Pop register additionally pops the top data entry out of the RxFIFO.
Page 921 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.9 Host Mode Receive Status Debug Read/Status Read and Pop Registers (GRXSTSR/GRXSTSP, R, Address = 0xEC00_001C, 0xEC00_0020) GRXSTSR/ Description Initial State GRXSTSP Reserved [31:21] - PktSts [20:17] Packet Status Indicates the status of the received packet. 4'b0010: IN data packet received •...
Page 922 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.10 Device Mode Receive Status Debug Read/Status Read and Pop Registers (GRXSTSR/GRXSTSP, R, Address = 0xEC00_001C, 0xEC00_0020) GRXSTSR/ Description Initial State GRXSTSP Reserved [31:25] 7'h3F [24:21] Frame Number 4'hF This is the least significant 4 bits of the (micro) frame number in which the packet is received on the USB.
Page 923 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.12 Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ, R/W, Address = 0xEC00_0028) The application programs the RAM size and the memory start address for the Non-Periodic TxFIFO. GNPTXFSIZ Description Initial State NPTxFDep [31:16] Non-Periodic TxFIFO Depth (For host mode) 16'h1F00 This value is in terms of 32-bit words.
Page 924 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.13 Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS, R, Address = 0xEC00_002C) This read-only register contains the free space information for the Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue. GNPTXSTS Description Initial State Reserved [31] 1'b0 NPTxQTop [30:24] Top of the Non-Periodic Transmit Request Queue.
Page 925 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.14 Core LPM Configuration Register (GLPMCFG, R/W, Address = 0xEC00_0054) This register controls the operation of the core’s LPM and HSIC capabilities. It also contains status bits pertaining to these features. GLPMCFG Description Initial State Reserved [31:28] - 4'b0...
Page 926 S5PC110_UM 5 USB2.0 HS OTG GLPMCFG Description Initial State the timer TL1TokenRetry. has expired. To stop the PHY clock, the application must set the Port Clock Stop bit, which asserts the PHY’s Suspend input pin. The application must rely on SlpSts and not ACK in CoreL1Res to confirm transition into sleep.
Page 927 S5PC110_UM 5 USB2.0 HS OTG GLPMCFG Description Initial State EnblSlpM For UTMI+ interface: The application uses this bit to control 1'b0 utmi_sleep_n assertion to the PHY in the L1 state. For the host, this bit is valid only in Local Device mode. •...
Page 928 S5PC110_UM 5 USB2.0 HS OTG 5.8.3.15 Host Periodic Transmit FIFO Size Register (HPTXFSIZ, R/W, Address = 0xEC00_0100) This register holds the size and the memory start address of the Periodic TxFIFO. HPTXFSIZ Description Initial State PTxFSize [31:16] Host Periodic TxFIFO Depth 16'h0300 This value is in terms of 32-bit words Minimum value is 16...
Page 929 S5PC110_UM 5 USB2.0 HS OTG 5.8.4 HOST MODE REGISTERS (HOST GLOBAL REGISTERS) These registers affect the operation of the core in the Host mode. Host mode registers must not be accessed in Device mode, as the results are undefined. Host Mode registers are categorized as follows: •...
Page 930 S5PC110_UM 5 USB2.0 HS OTG 5.8.4.2 Host Frame Interval Register (HFIR, R/W, Address = 0xEC00_0404) This register stores the frame interval information for the current speed to which the core has enumerated HFNUM Description Initial State Reserved [31:16] 16’h0 FrInt [15:0] Frame Interval 16'h0B8F...
Page 931 S5PC110_UM 5 USB2.0 HS OTG 5.8.4.4 Host Periodic Transmit FIFO/QUEUE Status Register (HPTXSTS, R, Address = 0xEC00_0410) This read-only register contains the free space information for the Periodic TxFIFO and the Periodic Transmit Request Queue. HPTXSTS Description Initial State PTxQTop [31:24] Top of the Periodic Transmit Request Queue 8'h0...
Page 932 S5PC110_UM 5 USB2.0 HS OTG 5.8.4.5 Host All Channels Interrupt Register (HAINT, R, Address = 0xEC00_0414) If a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the application using the Host Channels Interrupt bit of the Core Interrupt register. There is one interrupt bit per channel, up to a maximum of 16 bits.
Page 933 S5PC110_UM 5 USB2.0 HS OTG 5.8.5 HOST MODE REGISTERS ( HOST PORT CONTROL AND STATUS REGISTERS) 5.8.5.1 Host Port Control and Status Register (HPRT, R/W, Address = 0xEC00_0440) This register is available only in Host mode. Currently, the OTG Host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port.
Page 934 S5PC110_UM 5 USB2.0 HS OTG HPRT Description Initial State PrtRst Port Reset 1'b0 If the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete. 1'b0: Port not in reset •...
Page 935 S5PC110_UM 5 USB2.0 HS OTG HPRT Description Initial State PrtEnChng Port Enable/Disable Change R_SS_ 1'b0 The core sets this bit if the status of the Port Enable bit [2] of this register changes. PrtEna Port Enable R_SS_ 1'b0 A port is enabled by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the application clearing this bit.
Page 936 S5PC110_UM 5 USB2.0 HS OTG 5.8.6 HOST MODE REGISTERS (HOST CHANNEL-SPECIFIC REGISTERS) 5.8.6.1 Host Channel-n Characteristics Register (HCCHARn, R/W, Address = 0xEC00_0500+n*20h) Channel_number: 0 ≤ n ≤ 15 HCCHARn Description Initial State ChEna [31] Channel Enable 1'b0 S_SC This field is set by the application and cleared by the OTG host. 1'b0: Disables Channel •...
Page 937 S5PC110_UM 5 USB2.0 HS OTG HCCHARn Description Initial State Reserved [16] 1'b0 EPDir [15] Endpoint Direction Endpoint Type 1'b0 Indicates the transfer type selected. 1'b0: Out • 1'b1: In • EPNum [14:11] Endpoint Number 4'h0 Indicates the endpoint number on the device serving as the data source or sink.
Page 938 S5PC110_UM 5 USB2.0 HS OTG 5.8.6.3 Host Channel-n Interrupt Register (HCINTn, R/W, Address = 0xEC00_0508+n*20h) Channel_number: 0 ≤ n ≤ 15 This register indicates the status of a channel with respect to USB- and AHB-related events. The application must read this register if the Host Channels Interrupt bit of the Core Interrupt register is set. Before the application reads this register, it must first read the Host All Channels Interrupt register to get the exact channel number for the Host Channel-n Interrupt register.
Page 939 S5PC110_UM 5 USB2.0 HS OTG 5.8.6.4 Host Channel-n Interrupt Mask Register (HCINTMSKn, R/W, Address = 0xEC00_050C+n*20h) Channel_number: 0 ≤ n ≤ 15 This register reflects the mask for each channel status described in the previous section. • Mask interrupt : 1'b0 •...
Page 940 S5PC110_UM 5 USB2.0 HS OTG 5.8.6.5 Host Channel-n Transfer Size Register (HCTSIZn, R/W, Address = 0xEC00_0510+n*20h) Channel_number: 0 ≤ n ≤ 15 HCTSIZn Description Initial State DoPng [31] Do Ping 1'h0 Setting this field to 1 directs the host to do PING protocol. [30:29] 2'b0 The application programs this field with the type of PID to...
Page 941 S5PC110_UM 5 USB2.0 HS OTG 5.8.7 DEVICE MODE REGISTERS (DEVICE GLOBAL REGISTERS) These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. Some of them affect all the endpoints uniformly, while others affect only a specific endpoint. Device Mode registers fall into two categories: •...
Page 942 S5PC110_UM 5 USB2.0 HS OTG DCFG Description Initial State PerFrInt [12:11] Periodic Frame Interval 2'h0 Indicates the time within a (micro) frame at which the application must be notified using the End Of Periodic Frame Interrupt. This can be used to determine if all the isochronous traffic for that (micro) frame is complete.
Page 943 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.2 Device Control Register (DCTL, R/W, Address = 0xEC00_0804) DCTL Description Initial State Reserved [31:17] - 15'h0 NakOnBable [16] Set NAK automatically on babble (NakOnBble). The core 1'b0 sets NAK automatically for the endpoint on which babble is received IgnrFrmNum [15]...
Page 944 S5PC110_UM 5 USB2.0 HS OTG DCTL Description Initial State CGNPInNAK Clear Global Non-Periodic IN NAK 1'b0 A write to this field clears the Global Non-Periodic IN NAK. SGNPInNAK Set Global Non-Periodic IN NAK 1'b0 A write to this field sets the Global Non-Periodic IN NAK. The application uses this bit to send a NAK handshake on all non-periodic IN endpoints.
Page 945 S5PC110_UM 5 USB2.0 HS OTG DCTL Description Initial State RmtWkUpSig Remote Wakeup Signaling 1'b0 If the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1-15ms after setting it.
Page 946 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.3 Device Status Register (DSTS, R, Address = 0xEC00_0808) This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device ALL Interrupts (DAINT) register. DSTS Description Initial State Reserved...
Page 947 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.4 Device IN Endpoint Common Interrupt Mask Register (DIEPMSK, R/W, Address = 0xEC00_0810) This register works with each of the Device IN Endpoint Interrupt registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register is masked by writing to the corresponding bit in this register.
Page 948 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.5 Device OUT Endpoint Common Interrupt Mask Register (DOEPMSK, R/W, Address = 0xEC00_0814) This register works with each of the Device OUT Endpoint Interrupt registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupts for a specific status in the DOEPINTn register is masked by writing to the corresponding bit in this register.
Page 949 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.7 Device ALL Endpoints Interrupt Mask Register (DAINTMSK, R/W, Address = 0xEC00_081C) The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the application if an event occurs on a device endpoint. However, the Device all Endpoints Interrupt register bit corresponding to that interrupt remains set.
Page 950 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.10 Device Threshold Control Register (DTHRCTL, R/W, Address = 0xEC00_0830) Thresholding is not supported in Slave mode and so this register must not be programmed in Slave mode. DTHRCTL Description Initial State Reserved [31:28] - 4'h0 ArbPrkEn [27]...
Page 951 S5PC110_UM 5 USB2.0 HS OTG DTHRCTL Description Initial State The recommended value for ThrLen is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen). ISOThrEn ISO IN Endpoints Threshold Enable 1’b0 When this bit is set, the core enables thresholding for isochronous IN endpoints NonISOThrEn Non-ISO IN Endpoints Threshold Enable...
Page 952 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.11 Device IN Endpoint FIFO Empty Interrupt Mask Register (DIEPEMPMSK, R/W, Address = 0xEC00_0834) This register is used to control the IN endpoint FIFO empty interrupt generation (DIEPINTn.TxfEmp). • Mask interrupt: 1'b0 • Unmask interrupt: 1'b1 DVBUSPULSE Description Initial State...
Page 953 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.13 Device Control IN Endpoint 0 Control Register (DIEPCTL0, R/W, Address = 0xEC00_0900) This section describes the Control IN Endpoint 0 Control register. Nonzero control endpoints use registers for endpoints 1-15. DIEPCTL0 Description Initial State EPEna [31] Endpoint Enable...
Page 954 S5PC110_UM 5 USB2.0 HS OTG DIEPCTL0 Description Initial State NAKsts [17] NAK Status 1'b0 Indicates the following: 1'b0: The core is transmitting non-NAK handshakes based on • the FIFO status 1'b1: The core is transmitting NAK handshakes on this • endpoint If this bit is set, either by the application or core, the core stops transmitting data, even if there is data available in the TxFIFO.
Page 955 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.14 Device Control OUT Endpoint 0 Control Register (DOEPCTL0, R/W, Address =0xEC00_0B00) This section describes the Control OUT Endpoint 0 Control register. Nonzero control endpoints use registers for endpoints 1-15. DOEPCTL0 Description Initial State EPEna [31] Endpoint Enable R_WS_...
Page 956 S5PC110_UM 5 USB2.0 HS OTG DOEPCTL0 Description Initial State [17] NAK Status 1'b0 NAKsts Indicates the following: 1'b0: The core is transmitting non-NAK handshakes based • on the FIFO status 1'b1: The core is transmitting NAK handshakes on this • endpoint If application or the core sets this bit, the core stops receiving data, even if there is space in the RxFIFO to accommodate...
Page 957 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.15 Device Endpoint-n Control Register (DIEPCTLn/DOEPCTLn, R/W, Address = 0xEC00_0900+ n*20h, 0xEC00_0B00+ n*20h) Endpoint_number:1 ≤ n ≤ 15 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. DIEPCTLn/ Description Initial State...
Page 958 S5PC110_UM 5 USB2.0 HS OTG DIEPCTLn/ Description Initial State DOEPCTLn DATA0. This field is applicable both for Scatter/Gather DMA mode and non- Scatter/Gather DMA mode. SetEvenFr In non-Scatter/Gather DMA mode: Set Even (micro) frame (SetEvenFr) Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd (micro) frame (EO_FrNum) field to even (micro) frame.
Page 959 S5PC110_UM 5 USB2.0 HS OTG DIEPCTLn/ Description Initial State DOEPCTLn 2'b01: Isochronous • 2'b10: Bulk • 2'b11: Interrupt • NAKsts [17] NAK Status 1'b0 Applies to IN and OUT endpoints. Indicates the following: 1’b0: The core is transmitting non-NAK handshakes based on •...
Page 960 S5PC110_UM 5 USB2.0 HS OTG DIEPCTLn/ Description Initial State DOEPCTLn SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. Reserved [14:11] - 4'h0 [10:0] Maximum Packet Size 11'h0 Applies to IN and OUT endpoints. The application must program this field with the maximum packet size for the current logical endpoint.
Page 961 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.16 Device Endpoint-n Interrupt Register (DIEPINTn/DOEPINTn, R/W, Address = 0xEC00_0908 +n*20h, 0xEC00_0B08 +n*20h) Endpoint_number: 0 ≤ n ≤ 15 This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register if the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register is set.
Page 962 S5PC110_UM 5 USB2.0 HS OTG DIEPINTn/ Description Initial State DOEPINTn TxFEmp Transmit FIFO Empty This bit is valid only for IN Endpoints This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
Page 963 S5PC110_UM 5 USB2.0 HS OTG DIEPINTn/ Description Initial State DOEPINTn OUTTknEPdis OUT Token Received When Endpoint Disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
Page 964 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.17 Device Endpoint 0 Transfer Size Register (DIEPTSIZ0, R/W, Address = 0xEC00_0910) The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core modifies this register.
Page 965 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.18 Device OUT Endpoint 0 Transfer Size Register (DOEPTSIZ0, R/W, Address = 0xEC00_0B10) DOEPTSIZ0 Description Initial State Reserved [31] 1'b0 SUPCnt [30:29] SETUP Packet Count 2'h0 This field specifies the number of back-to-back SETUP data packets the endpoint can receive.
Page 966 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.19 Device Endpoint-n Transfer Size Register (DIEPTSIZn/DOEPTSIZn, R/W, Address = 0xEC00_0910 +n*20h, 0xEC00_0B10 +n*20h) Endpoint_number: 1 ≤ n ≤ 15 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register.
Page 967 S5PC110_UM 5 USB2.0 HS OTG DIEPTSIZn/ Description Initial State DOEPTSIZn (maximum size or short packet) is written to the RxFIFO. Transfer Size XferSize [18:0] 19'h0 This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data.
Page 968 S5PC110_UM 5 USB2.0 HS OTG 5.8.7.21 Device IN Endpoint Transmit FIFO Status (DTXFSTSn, R/W, Address = 0xEC00_0918 +n*20h) Endpoint_number: 0 ≤ n ≤ 15 This read-only register contains the free space information for the Device IN endpoint TxFIFO DTXFSTSn Description Initial State Reserved [31:16] -...
Page 969 This chapter defines the interface between the Base-band Modem (like MSM) and the Application Processor to facilitate data-exchange between these two devices. To facilitate data-exchange, S5PC110 include a dual-ported SRAM buffer (on-chip). To access SRAM buffer, the Modem chip uses a typical asynchronous-SRAM interface.
Page 970 There are two address views for MODEMIF, namely, MSM address (ADR) for MODEM chip, and AHB address for S5PC110. AHB address is twice the size of ADR. For example, 0x3FFC at AHB bus is 0x1FFE at ADR. helps you to understand it.
Page 971 S5PC110_UM 6 MODEM INTERFACE 6.4 ADDRESS MAPPING Internal DPSRAM (MODEM view ) ( ARM view) Slot 0 0 (MSBM, 0xED000000 ) Slot 1 2 (MSBM, 0xED000002 ) Slot 2 4 (MSBM, 0xED000004 ) 2-byte ( 16-bit) 1- byte ( 8- bit) addressing addressing 1FFE...
Page 972 S5PC110_UM 6 MODEM INTERFACE 6.5 TIMING DIAGRAM 6.5.1 STANDARD MODE WRITE, READ TIMING AVWR CSVWR DSUWR DHWR DATA Figure 6-3 Modem Interface Write Timing Diagram (Standard Mode) Table 6-2 Modem Interface Write Timing (Standard Mode) Parameter Description Min (ns) Max (ns) Notes Address valid to address invalid 16 ns...
Page 973 S5PC110_UM 6 MODEM INTERFACE AVRD CSVRD CSRD RDDV DATA ACSDV Figure 6-4 Modem Interface Read Timing Diagram (Standard Mode) Table 6-3 Modem Interface Read Timing (Standard Mode) Parameter Description Min (ns) Max (ns) Notes Address valid to address invalid 50 ns AVRD Address hold 0 ns...
Page 974 S5PC110_UM 6 MODEM INTERFACE 6.5.2 ADDRESS MUXED MODE WRITE, READ TIMING Figure 6-5 Modem Interface Write Timing Diagram (Address Muxed mode) Table 6-4 Modem Interface Write Timing (Address Muxed mode) Parameter Description Min (ns) Max (ns) Notes Address valid setup 15 ns AVDS Address valid hold...
Page 975 S5PC110_UM 6 MODEM INTERFACE Figure 6-6 Modem Interface Read Timing Diagram (Address Muxed mode) Table 6-5 Modem Interface Read Timing (Address Muxed mode) Parameter Description Min (ns) Max (ns) Notes Address valid setup 15 ns AVDS Address valid hold 5 ns AVDH Address valid duration 15 ns...
Page 976 FIFO managements, and so on. The software should be responsible for required functionalities for the data exchange between the modem chip and the S5PC110, namely, data exchange protocol, data buffer managements, and so on.
Page 977 S5PC110_UM 6 MODEM INTERFACE 6.8 REGISTER DESCRIPTION 6.8.1 REGISTER MAP Register Address Description Reset Value MSBM 0xED00_0000 ~ Specifies the MODEM I/F SRAM Buffer 0xED00_3FFC Memory (AP side) INT2AP 0xED00_8000 Specifies the Interrupt Request to AP 0x00003FFE Register INT2MSM 0xED00_8004 Specifies the Interrupt Request to MSM 0x00003FFC Modem Register...
Page 978 1 to the corresponding bit field. NOTE: It is recommended that S5PC110 write data with half-word access on the interrupt port because S5PC110 overwrites the data in INT2AP if there are INT2AP and INT2MSM sharing the same word.
Page 979 S5PC110_UM 6 MODEM INTERFACE 6.8.1.3 Modem Interface Control Register (MIFCON, R/W, Address = 0xED00_8008) MIFCON Description Initial State Reserved [31:21] Fixed [20] Should write as 1 DMARXREQEN_1 [19] Enables MSM Write DMA Request (RX 1) to AP (DMA Controller) DMARXREQEN_0 [18] Enables MSM Write DMA Request (RX 0) to AP (DMA Controller)
Page 980 Write access to this register with any data will clear the interrupt pending register of MSM modem interface. NOTE: The interrupt controllers of S5PC110 receive level-triggered type interrupt requests. Therefore, interrupt requests from MSM interface are maintained until the interrupt service routine clears the interrupt pending register by writing any data into this register.
Page 981 SD/MMC CONTROLLER This chapter describes the Secure Digital (SD/ SDIO), MultiMediaCard (MMC), CE-ATA host controller and related registers supported by S5PC110 RISC microprocessor. 7.1 OVERVIEW OF SD/ MMC CONTROLLER The SD/ MMC host controller is a combo host for Secure Digital card and MultiMediaCard. This host controller is based on SD Association’s (SDA) Host Standard Specification.
Page 982 S5PC110_UM 7 SD/MMC CONTROLLER 7.3 BLOCK DIAGRAM OF SD/ MMC CONTROLLER HCLK SDCLK BaseCLK Domain Domain Status Clock Control INTREQ Status System CMDRSP packet (AHB) Line Control Control Control FIFO AHB slave I/F Control Control DPSRAM Status controller DATA AHB master packet Figure 7-1 SDMMC Clock Domain...
Page 983 S5PC110_UM 7 SD/MMC CONTROLLER 7.4 OPERATION SEQUENCE This section defines basic operation flow chart divided into several sub sequences. "Wait for interrupts" is used in the flow chart. This means the Host Driver waits until specified interrupts are asserted. If already asserted, then follow the next step in the flow chart.
Page 984 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.2 SD CLOCK SUPPLY SEQUENCE Figure 7-3 SD Clock Supply Sequence The sequence to set SD Clock to a SD card is shown in . The clock is enabled before one of the Figure 7-3 following actions: −...
Page 985 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.3 SD CLOCK STOP SEQUENCE Figure 7-4 SD Clock Stop Sequence The flow chart to stop the SD Clock is shown in The Host Driver does not stop the SD Clock if a SD Figure 7-4 transaction takes place on the SD Bus -- namely, either Command Inhibit (DAT) or Command Inhibit (CMD) in the Present State register is set to 1.
Page 986 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.4 SD CLOCK FREQUENCY CHANGE SEQUENCE START ( 1 ) SD Clock Stop ( 2 ) SD Clock Supply Figure 7-5 SD Clock Frequency Change Sequence The sequence to change SD Clock frequency is shown in .
Page 987 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.5 SD BUS POWER CONTROL SEQUENCE START (1 ) Get the support voltage of the Host Controller (2 ) Set SD Bus voltage select with supported maximum voltage (3 ) Set SD Bus Power (4 ) Get OCR value of the SD Card ( 5 ) no change...
Page 988 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.6 CHANGE BUS WIDTH SEQUENCE START (1 ) Disable Card Interrupt in Host SD Memory Only Card ? (6 ) SD Memory Only Card ? (3 ) Mask Card Interrupt in Card ( 7) Enable Card Interrupt in Card (4 ) ( 8) Change Bit Mode in Card...
Page 989 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.7 TIMEOUT SETTING FOR DAT LINE START ( 1) Calculate a Divisor for detecting Timeout ( 2) Set Timeout Detection Timer Figure 7-8 Timeout Setting Sequence In order to detect timeout errors on DAT line, the Host Driver executes the following two steps before any SD transaction.
Page 990 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.8 SD TRANSACTION GENERATION This section describes the sequence to generate and control various kinds of SD transactions. SD transactions are classified into three cases, namely: 1. Transactions that do not use the DAT line. 2. Transactions that use the DAT line for the busy signal. 3.
Page 991 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.9 SD COMMAND ISSUE SEQUENCE START CMD Line used Check Command Inhibit (CMD ) ? CMD Line free Issue the Command with the Busy ? Issue Abort Command ? DAT Line used Check Command Inhibit ( DAT ) ? DAT Line free New command can be issued Set Argument Reg...
Page 992 S5PC110_UM 7 SD/MMC CONTROLLER Steps to set Timeout: 1. Check Command Inhibit (CMD) in the Present State register. Repeat this step until Command Inhibit (CMD) is 0. If Command Inhibit (CMD) is 1, the Host Driver does not issue a SD Command. 2.
Page 993 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.10 COMMAND COMPLETE SEQUENCE The sequence to complete the SD Command is shown in . The Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 following errors can occur during this sequence: Command Index/ End bit/ CRC/ Timeout Error. Steps to complete the SD command: 1.
Page 994 S5PC110_UM 7 SD/MMC CONTROLLER START Wait for Command Complete Int Command Complete Int occur Clear Command Complete Status Get Response Data ( 4) Command with Transfer Complete Int ? Wait for Transfer Complete Int Transfer Complete Int occur Clear Transfer Complete Status ( 7) Error Check Response Data ?
Page 995 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.11 TRANSACTION CONTROL WITH DATA TRANSFER USING DAT LINE Depending on whether DMA (optional) is used or not, there are two execution methods. The sequence without using DMA is shown in and the sequence using DMA is shown in Figure 7-11 Figure 7-12 In addition, the sequences for SD transfers are basically classified according to how the number of blocks is...
Page 996 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.12 SEQUENCE WITHOUT USING DMA START Set Block Size Reg Set Command Reg Set Block Count Reg Wait for Command Complete Interrupt Command Complete Interrupt occur Set Argument Reg Clear Command Complete Status Set Transfer Mode Reg Get Response Data write read...
Page 997 S5PC110_UM 7 SD/MMC CONTROLLER 1. Set the value corresponding to the executed data byte length of one block to Block Size register. 2. Set the value corresponding to the executed data block count to Block Count register. 3. Set the value corresponding to the issued command to Argument register. 4.
Page 998 S5PC110_UM 7 SD/MMC CONTROLLER 7.4.13 SEQUENCE USING DMA START Set System Address Reg (10) Set Block Size Reg Wait for Transfer Complete Int and DMA Interrupt Set Block Count Reg Transfer Complete (11) Interrupt occur Check Interrupt Status Set Argument Reg DMA Interrupt (12) occur...
Page 999 S5PC110_UM 7 SD/MMC CONTROLLER 7. Wait for the Command Complete Interrupt. 8. Write 1 to the Command Complete (STACMDCMPLT) in the Normal Interrupt Status register to clear this bit. 9. Read Response register and get necessary information in accordance with the issued command. 10.
Page 1000 S5PC110_UM 7 SD/MMC CONTROLLER 7.5 ABORT TRANSACTION To perform Abort transaction issue CMD12 (Stop Command) for a SD memory and issue CMD52 for a SDIO card. There are two cases where the Host Driver needs to issue an Abort Transaction. The first case is if the Host Driver stops Infinite Block Transfers.
Page 1001 S5PC110_UM 7 SD/MMC CONTROLLER 7.6 DMA TRANSACTION DMA allows a peripheral to read and write memory without intervention from the CPU. DMA executes one SD command transaction. Host Controllers that support DMA supports both single block and multiple block transfers. The System Address register points to the first data address, and data is then accessed sequentially from that address.

Samsung S5PC110 Manual

Section 1

1 Overview of S5PC110

2 Memory Map

Section 2

1 Chip ID

2 General Purpose Input/ Output

3 Clock Controller

4 Power Management

5 Intelligent Energy Management

6 Booting Sequence

Section 3

1 Bus Configuration

2 Coresight

3 Access Controller (TZPC)

Section 4

Section 5

1 DRAM Controller

2 SROM Controller

3 Onenand Controller

4 NAND Flash Controller

5 Compact Flash Controller

6 External Bus Interface

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