Samsung S3C6400X User Manual page 573

CAMERA INTERFACE
CLOCK DOMAIN
Camera Interface has two clock domains. The one is the system bus clock, which is HCLK. The other is the pixel
clock, which is PCLK. The system clock must be faster than pixel clock. As highlighted in figure 20- 7, CAMCLK
must be divided from the fixed frequency like APLL or MPLL clock. If external clock oscillator is used, CAMCLK
must be floated. Internal scaler clock is system clock. It is not mandatory for two clock domains to be
synchronized with each other. Other signals as PCLK must be similarly connected to shimitt-triggered level shifter.
(f or f )/d
mpll apll
Normally use
External
Camera
Processor
External MCLK
Preliminary product information describe products that are in development,
20-8
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
XciCLK
Schmit-triggered
Level-shifter
XciPCLK
Figure 20-7. CAMERA INTERFACE clock generation
S3C6400X RISC MICROPROCESSOR
APLL or
MPLL
f or
mpll
f
apll
1/1,1/2,1/3...~
Divide
1/16
Counter
HCLK
CAMIF
Variable
MPLL
Freq.
f
mpll
Divide
Counter
f /d
mpll