Samsung S3C6400X User Manual page 127

S3C6400X RISC MICROPROCESSOR
SPECIAL FUNCTION REGISTERS
SROM BUS WIDTH & WAIT CONTRL REGISTER(SROM_BW)
Register Address
SROM_BW 0x70000000
SROM_BW Bit
Reserved [31:24]
ByteEnable5 [23]
WaitEnable5 [22]
Reserved [21]
DataWidth5 [20]
ByteEnable4 [19]
WaitEnable4 [18]
Reserved [17]
DataWidth4 [16]
ByteEnable3 [15]
WaitEnable3 [14]
Reserved [13]
DataWidth3 [12]
ByteEnable2 [11]
[10]
WaitEnable2
Reserved [9]
R/W
SROM Bus width & wait control
R/W
Reserved
nWBE / nBE(for UB/LB) control for Memory Bank5
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
Wait enable control for Memory Bank5
0 = WAIT disable
Reserved
Data bus width control for Memory Bank5
0 = 8-bit
nWBE / nBE(for UB/LB) control for Memory Bank4
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
Wait enable control for Memory Bank4
0 = WAIT disable
Reserved
Data bus width control for Memory Bank4
0 = 8-bit
nWBE / nBE(for UB/LB) control for Memory Bank3
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
Wait enable control for Memory Bank3
0 = WAIT disable
Reserved
Data bus width control for Memory Bank3
0 = 8-bit
nWBE / nBE(for UB/LB) control for Memory Bank2
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
Wait enable control for Memory Bank2
0 = WAIT disable
Reserved
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
1 = WAIT enable
1 = 16-bit
1 = WAIT enable
1 = 16-bit
1 = WAIT enable
1 = 16-bit
1 = WAIT enable
SROM CONTROLLER
Reset Value
0x0000_000x
Initial State
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6-5