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S3C6400X RISC MICROPROCESSOR
Rx module:
Status register
FIFO status (fifo full, fifo empty, fifo write point, fifo read point)
MIPI status (internal status : current status & next status)
Configuration register 0
Operation mode select (stream mode or frame mode)
Fixed channel ID mode
Number of channel
Generated Error clear
RxACK state timer & enable
Rx state timer
Configuration register 1
Rx FIFO clear
Rx FIFO timer & enable
Interrupt source register
Rx FIFO full
Rx FIFO timeout
Data Receiving Done
Break frame received
Break frame receiving error
RxACK state timeout
Missed clock input
Added clock input
Software reset register
Channel ID register
Data register
Rx FIFO input
Rx FIFO size (Flip-Flop FIFO, not memory)
32bit width X 64 depth (256Byte)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MIPI HSI
28-3
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