Samsung S3C6400X User Manual page 332

S3C6400X RISC MICROPROCESSOR
REGISTER DESCRIPTIONS
IRQ Status Register, VICIRQSTATUS
Bits Name
[31:0] IRQStatus
FIQ Status Register, VICFIQSTATUS
Bits Name
[31:0] FIQStatus
Raw Interrupt Status Register, VICRAWINTR
Bits Name
[31:0] RawInterrupt
Interrupt Select Register, VICINTSELECT
Bits Name
[31:0] IntSelect
Type Function
R Show the status of the interrupts after masking by the
VICINTENABLE and VICINTSELECT Registers:
0 = interrupt is inactive (reset)
1 = interrupt is active.
There is one bit of the register for each interrupt source.
Type Function
R Show the status of the FIQ interrupts after masking by
the VICINTENABLE and VICINTSELECT Registers:
0 = interrupt is inactive (reset)
1 = interrupt is active.
There is one bit of the register for each interrupt source.
Type Function
R Show the status of the FIQ interrupts before masking by
the VICINTENABLE and VICINTSELECT Registers:
0 = interrupt is inactive before masking
1 = interrupt is active before masking
Because this register provides a direct view of the raw
interrupt inputs, the reset value is unknown.
There is one bit of the register for each interrupt source.
Type Function
Selects type of interrupt for interrupt request:
RW
0 = IRQ interrupt (reset)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
VECTORED INTERRUPT CONTROLLER
12-9