Samsung S3C6400X User Manual page 851

USB2.0 HS OTG
HubAddr
PrtAddr
HOST CHANNEL-n INTERRUPT REGISTER (HCINTn)
Channel_number : 0≤ n≤ 15
This register indicates the status of a channel with respect to USB- and AHB-related events. The application must
read this register when the Host Channels Interrupt bit of the Core Interrupt register is set. Before the application
can read this register, it must first read the Host All Channels Interrupt register to get the exact channel number
for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the HAINT and GINTSTS registers.
Register Address
HCINTn 0x7C00_0508
+n*20h
HCINTn
[31:11]
DataTglErr
FrmOvrun
BblErr
XactErr
NYET
ACK
NAK
STALL
AHBErr
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-44
Specifications and information herein are subject to change without notice.
transaction.
· 2'b00 : Mid. This is the middle payload of this
transaction.
· 2'b01 : End. This is the last payload of this
transaction.
[13:7] R_W Hub Address
This field holds the device address of the transaction
translator's hub.
[6:0] R_W Port Address
This field is the port number of the recipient
transaction translator.
R/W
R/W
Bit R/W
Reserved
[10] R_SS_ Data Toggle Error
WC
[9] R_SS_ Frame Overrun
WC
[8] R_SS_ Babble Error
WC
[7] R_SS_ Transaction Error
WC
[6] R_SS_ NYET Response Received Interrupt
WC
[5] R_SS_ ACK Response Received Interrupt
WC
[4] R_SS_ NAK Response Received Interrupt
WC
[3] R_SS_ STALL Response Received Interrupt
WC
[2] R_SS_ AHB Error
Description
Host Channel-n interrupt Register
Description
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial State
7'h0
7'h0
32 bits
21'h0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0