Samsung S3C6400X User Manual page 977

SPI CONTROLLER
IntEnTxOverrun
IntEnTxUnderrun
IntEnRxFifoRdy
IntEnTxFifoRdy
Register
SPI_STATUS(Ch0)
SPI_STATUS(Ch1)
SPI_STATUS
TX_done
Trailing_byte
RxFifoLvl
TxFifoLvl
RxOverrun
RxUnderrun
TxOverrun
TxUnderrun
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
29-8
Specifications and information herein are subject to change without notice.
0: Disable
R/W
[3]
0: Disable
Interrupt Enable for TxUnderrun. In slave
mode, this bit must be clear first after turning
R/W
on slave TX path.
[2]
0: Disable
Interrupt Enable for RxFifoRdy(INT mode)
R/W
[1]
0: Disable
Interrupt Enable for TxFifoRdy(INT mode)
R/W
[0]
0: Disable
Address R/W
0x7F00B014 R SPI status register
0x7F00C014 R SPI status register
Bit
Indication of transfer done in Shift register
0 : all case except blow case
[21] R
1 : when tx fifo and shift register are empty
[20] R Indication that trailing count is zero
Data level in RX FIFO
R
[19:13]
0 ~ 7'h40 byte
Data level in TX FIFO
R
[12:6]
0 ~ 7'h40 byte
Rx Fifo overrun error
R
[5]
0: no error,
Rx Fifo underrun error
R
[4]
0: no error,
Tx Fifo overrun error
R
[3]
0: no error,
R Tx Fifo underrun error
[2]
S3C6400X RISC MICROPROCESSOR
Interrupt Enable for TxOverrun
Description
Description
1: overrun error
1: underrun error
1: overrun error
1:Enable
1'b0
1:Enable
1'b0
1:Enable
1'b0
1:Enable
1'b0
1:Enable
Reset Value
0x0
0x0
Initial State
1'b0
1'b0
7'b0
7'b0
1'b0
1'b0
1'b0
1'b0