Samsung S3C6400X User Manual page 352

S3C6400X RISC MICROPROCESSOR
SECURITY SUB-SYSTEM AES MODULE
AES_CTRL
Register Address
AES_Rx_CTRL 0x7D10_0000
SKEY_IDx
WrPrivMismatch [31]
RdPrivMismatch [30]
Reserved [29:11]
AesOutReady [10]
AesInReady
AesContDecOn
CtrWidth [7:6]
AesOpMode [5:4]
AesOpDirection
AesKeyMode [2:1]
AesOpEnable
R/W
R/W AES Control / Status Register
Bit
SFR Write Access Privilege Mismatch Status bit. If set to '1',
SFR Write Access Privilege Mismatch is occurred.
SFR Read Access Privilege Mismatch Status bit. If set to '1',
SFR Read Access Privilege Mismatch is occurred.
Reserved
If set to '1', AES Output Buffer is Full, and ARM or Rx FiFo is
permitted to Read current 128bits result data
If set to '1', AES Input Buffer is Empty, and ARM or Rx FiFo is
[9]
permitted to write next 128bits data.
Continuous Decryption Enable Bits
[8] 0 : Decryption Key is changed
1 : Decryption Key is not changed
Counter Mode Counter Width Bits
00 : 16Bits Counter
10 : 64Bits Counter
AES Operation Mode Selection Bits
00 = reserved
10 = CBC Mode
AES Operation Direction Selection Bit.
[3]
0 : Encryption
AES Key Mode Selection Bits.
00 : 128bits
10 : 256bits
If set to '1', AES starts operation by ARM. If the aes_op_done
[0]
is generated, It becomes '0'.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
01 : 32Bits Counter
11 = Reserved
01 = ECB Mode
11 = CTR Mode
1 : Decryption
01 : 192bits
11 = reseved
SECURITY SUB-SYSTEM
Reset Value
0x0000_0200
Initial State
0b
0b
0x000000
0b
1b
0b
00b
00b
0b
00b
0b
13-15