Samsung S3C6400X User Manual page 141

S3C6400X RISC MICROPROCESSOR
PIPELINE READ/WRITE AHEAD COMMAND
When a pipeline read-ahead or write-ahead command is received, and the controller is idle, this command will
initiate a load operation immediately into one of the dataram buffers of the memory device. Note that the read-
ahead command does NOT return the data to the AHB interface, and the write-ahead command does NOT write
data to the flash address. The read data is loaded and read data will be returned to the AHB port only when map
01 commands are issued to read this data. Similarly, the write data is loaded and will be written to the flash only
when map 01 commands are issued to write this data.
On read-ahead commands, the controller internally manages the read operations required. The controller will
issue cache reads to the Flash memory device for each page requested. If the transfer_spare register is set, then
the main data area and the spare area will both be transferred to the memory controller during a pipeline read-
ahead request.
Pipeline read-ahead commands may be entered sequentially, and pipeline write-ahead commands may be
entered sequentially. If all of the data has been read/written for the existing read-ahead/write-ahead command, a
pipelined read-ahead command may be followed by a pipelined write-ahead command, and vice versa.
If a current group of reads or writes is in process, the memory controller will hold off the new command until that
set of operations is completed. The OneNAND flash memory controller may have up to three read-ahead or write-
ahead commands pending in addition to the one being executed. The controller will not return to the idle state
until all read-ahead pipelined data has been read from the buffer or all write-ahead data has been written to
memory though map 01 commands.
Pipelined read-ahead or write-ahead takes precedence over register programming operations.
• Set Up a Single Area for Pipelined Read-Ahead
The procedure to set up an area for pipelined read-ahead is as follows:
1. The user must set the CMD_MAP to "Map 10" and set the starting address of the block to pre-read in the FBA,
FPA and FSA of the address.
2. The command type must be set to "Write" and the datain bus must be driven with a value of 0x40PP, where the
"0" sets this command as a read-ahead and PP is the number of pages to pre-read.
3. To read the data, the you must issue Map 01 commands to the memory controller with the same starting
address and the desired page(s). If the read command received following a pipeline read-ahead request is not to
a page pre-read, then an interrupt bit will be set and the pipeline read/write-ahead registers will be cleared. A new
pipeline read-ahead request must be issued to re-load the same data.
4. All of the data that was pre-read must be read through Map 01 commands before the controller will return to the
idle state.
Note: A PIPELINED READ-AHEAD OR WRITE-AHEAD FOR A SINGLE AREA MUST REQUEST AT LEAST 2
PAGES.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ONENAND CONTROLLER
7-11