Samsung S3C6400X User Manual page 824

S3C6400X RISC MICROPROCESSOR
OTG RESET CONTROL REGISTER (ORSTCON)
Register Address
ORSTCON 0x7C10_0008
ORSTCON
phylnk_sw_rst
link_sw_rst
phy_sw_rst
Figure 26-3. OTG PHY Clock Path
R/W
R/W
Bit R/W
[31:3] Reserved
[2] R_W OTG Link Core phy_clock domain S/W Reset
[1] R_W OTG Link Core hclk domain S/W Reset
OTG PHY 2.0 S/W Reset
[0] R_W
The phy_sw_rst signal must be asserted for at least
10us
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
OTG Reset Control Register
Description
USB2.0 HS OTG
Reset Value
32 bits
Initial State
29'h0
1'b0
1'b0
1'b1
26-17