Table of Contents
Advertisement
S3C6400X RISC MICROPROCESSOR
MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER
Register
IICADD
0x7F004008
IICADD
Bit
Slave address
[7:0]
MULTI-MASTER IIC-BUS TRANSMIT/RECEIVE DATA SHIFT (IICDS) REGISTER
Register
IICDS
0x7F00400C
IICDS
Bit
Data shift
[7:0]
Address
R/W
R/W
7-bit slave address, latched from the IIC-bus.
When serial output enable = 0 in the IICSTAT, IICADD is write-
enabled. The IICADD value can be read any time, regardless of
the current serial output enable bit (IICSTAT) setting.
Slave address : [7:1]
Not mapped
: [0]
Address
R/W
R/W
8-bit data shift register for IIC-bus Tx/Rx operation.
When serial output enable = 1 in the IICSTAT, IICDS is write-
enabled. The IICDS value can be read any time, regardless of the
current serial output enable bit (IICSTAT) setting.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
IIC-Bus address register
Description
Description
IIC-Bus transmit/receive data shift register
Description
IIC-BUS INTERFACE
Reset Value
0xXX
Initial State
XXXXXXXX
Reset Value
0xXX
Initial State
XXXXXXXX
30-13
Advertisement
Table of Contents
