Samsung S3C6400X User Manual page 924

HSMMC CONTROLLER
StaCCS [9]
Command Complete Signal Interrupt Status bit is for CE-ATA interface mode.
[8]
sample delays between the interrupt signal from the SD card and the interrupt
When this status has been set and the Host Driver needs to start this interrupt
register must be set to 0 in order to clear the card interrupt statuses latched in
the Host Controller and to stop driving the interrupt signal to the Host System.
[7]
Because the card detect state may possibly be changed when the Host Driver
[6]
Because the card detect state may possibly be changed when the Host Driver
[5]
[4]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-48
Specifications and information herein are subject to change without notice.
'1' = Read Wait Interrupt Not Occurred
Note: After checking response for the suspend command, release Read Wait
interrupt status manually if BS = 0
CCS Interrupt Status (RW1C)
'1' = CCS Interrupt Not Occurred
Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD
card interrupt factor. In 1-bit mode, the Host Controller shall detect the Card
Interrupt without SD Clock to support wakeup. In 4-bit mode, the card
interrupt signal is sampled during the interrupt cycle, so there are some
to the Host System. It is necessary to define how to handle this delay.
service, Card Interrupt Status Enable in the Normal Interrupt Status Enable
After completion of the card interrupt service (It must reset interrupt factors in
the SD card and the interrupt signal may not be asserted), set Card Interrupt
Status Enable to 1 and start sampling the interrupt signal again. (ROC,
This status is set if the Card Inserted in the Present State register changes
from 1 to 0. When the Host Driver writes this bit to 1 to clear this status, the
status of the Card Inserted in the Present State register must be confirmed.
clear this bit and interrupt event may not be generated. (RW1C)
'0' = Card state stable or Debouncing
This status is set if the Card Inserted in the Present State register changes
from 0 to 1. When the Host Driver writes this bit to 1 to clear this status, the
status of the Card Inserted in the Present State register must be confirmed.
clear this bit and interrupt event may not be generated. (RW1C)
'0' = Card state stable or Debouncing
This status is set if the Buffer Read Enable changes from 0 to 1. Refer to the
Buffer Read Enable in the Present State register. (RW1C)
'0' = CCS Interrupt Occurred
Card Interrupt
RW1C)
'1' = Generate Card Interrupt
'0' = No Card Interrupt
Card Removal
'1' = Card removed
Card Insertion
'1' = Card inserted
Buffer Read Ready
'1' = Ready to read buffer
'0' = Not ready to read buffer
Buffer Write Ready
S3C6400X RISC MICROPROCESSOR
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