Samsung S3C6400X User Manual page 378

DISPLAY CONTROLLER
2BPP display(Palette)
(BSWP = 0, HWSWP = 0)
D [31:30]
000H P1
004H P17
008H P33
...
D [15:14]
000H P9
004H P25
008H P41
...
Note:
1. If ALPHAPAL is enabled, then the MSB of Palette memory is acting as a AEN bit.
AEN = 0 : Select ALPHA0
AEN = 1 : Select ALPHA1
If per-pixel blending is set, then this pixel would be blended with alpha value selected by AEN.
Alpha value is selected by SFR value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G,
ALPHA1_B. For more information refer to description of SFR.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
14-16
Specifications and information herein are subject to change without notice.
[29:28] [27:26] [25:24]
P2 P3
P18 P19
P34 P35
[13:12] [11:10]
P10 P11
P26 P27
P42 P43
S3C6400X RISC MICROPROCESSOR
[23:22] [21:20]
P4 P5 P6
P20 P21 P22
P36 P37 P38
[9:8] [7:6] [5:4]
P12 P13 P14
P28 P29 P30
P44 P45 P46
[19:18] [17:16]
P7 P8
P23 P24
P39 P40
[3:2] [1:0]
P15 P16
P31 P32
P47 P48