Samsung S3C6400X User Manual page 934

HSMMC CONTROLLER
ERROR INTERRUPT SIGNAL ENABLE REGISTER
This register is used to select which interrupt status is notified to the Host System as the interrupt. These status
bits all share the same 1 bit interrupt line. To enable interrupt generate set any of this bit to 1.
Register
ERRINTSIGEN0 0x7C20003A
ERRINTSIGEN1 0x7C30003A
ERRINTSIGEN2 0x7C40003A
Name Bit
[15:9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Detailed documents are to be copied from SD Host Standard Specification.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-58
Specifications and information herein are subject to change without notice.
Address R/W
R/W
R/W
R/W
Reserved
Auto CMD12 Error Signal Enable
'1' = Enabled
'0' = Masked
Current Limit Error Signal Enable
This function is not implemented in this version.
'1' = Enabled
'0' = Masked
Data End Bit Error Signal Enable
'1' = Enabled
'0' = Masked
Data CRC Error Signal Enable
'1' = Enabled
'0' = Masked
Data Timeout Error Signal Enable
'1' = Enabled
'0' = Masked
Command Index Error Signal Enable
'1' = Enabled
'0' = Masked
Command End Bit Error Signal Enable
'1' = Enabled
'0' = Masked
Command CRC Error Signal Enable
'1' = Enabled
'0' = Masked
Command Timeout Error Signal Enable
'1' = Enabled
'0' = Masked
Description
Error Interrupt Signal Enable Register
(Channel 0)
Error Interrupt Signal Enable Register
(Channel 1)
Error Interrupt Signal Enable Register
(Channel 2)
Description
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial Value
0
0
0
0
0
0
0
0
0
0
0x0
0x0
0x0