Samsung S3C6400X User Manual page 349

SECURITY SUB-SYSTEM
SECURITY SUB-SYSTEM TX FIFO MODULE
FIFO-TX CONTROL REGISTER
Register Address
FTx_Ctrl 0x7D80_0000
FTx_Ctrl
WrPrivError
RdPrivError
Reserved [29:28]
Full
Empty
Done
Running
Wd2Read [23:16]
Wd2Write
Src_Module
Host_Rd_En
Host_Wr_En
Reset
ERROR_En
Start
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
13-12
Specifications and information herein are subject to change without notice.
R/W
R/W FIFO-Tx Control/Status Reg. (Only MSB 16-bit readable)
Bit
Sets to 1 if write access to FIFO-Tx has resulted in a privilege
[31] error (e.g. Host or the command are not allowed to access
FIFO-Tx).
Sets to 1 if read access to FIFO-Tx has resulted in a privilege
[30] error (e.g. Host or the command are not allowed to access
FIFO-Tx).
Reserved
[27] Sets to 1 if FIFO-Tx buffer (FTx_RdBuf) is full.
[26] Sets to 1 if FIFO-Tx buffer (FTx_RdBuf) is empty.
Sets to 1 if FIFO-Tx has finished transferring FTx_MLen
[25]
words of data from the source.
Sets to 1 if FIFO-Tx is transferring data from the source or
[24] waiting for source output buffer is ready. Sets to 1 when
FTx_Start bit resets to 0.
Number of words that can be read from FIFO memory
(FTx_RdBuf)
Number of words that can be written to FIFO memory
[15:8]
(FTx_RdBuf)
Source module selection.
[7:6] 00 : AES
10: SHA-1/PRNG
[5] Enables Host read from FTx_Ctrl[31:16] and FTx_MLenCnt.
[4] Enables Host read from FTx_RdBuf
Stops current FIFO-Tx transfer and resets FSM and all the
[2]
register.
Enables ERROR response via HRESP port when host tries to
[1] access FIFO-Tx and access is not enabled by FTx_Ctrl[4] or
[5].
FIFO-Tx transfer start bit. Resets to 0 when internal FSM
[0]
starts transferring data to destination.
S3C6400X RISC MICROPROCESSOR
Description
Description
01:DES/3DES
11: reserved
Reset Value
0x0400_2000
Initial State
0b
0b
00b
0b
1b
0b
0b
0x00
0x20
0b
0b
0b
0b
0b
0b