Samsung S3C6400X User Manual page 66

S3C6400X RISC MICROPROCESSOR
INDIVIDUAL REGISTER DESCRIPTIONS
PLL Control Registers
S3C6400 has three internal PLL's, which are APLL, MPLL, and EPLL. They are controlled by the following seven
special registers.
REGISTER
APLL_LOCK
MPLL_LOCK
EPLL_LOCK
APLL_CON 0x7E00_F00C
MPLL_CON
EPLL_CON0
EPLL_CON1
A PLL requires locking period when input frequency is changed or frequency division (multiplication) values are
changed. PLL_LOCK register specifies this locking period, which is based on PLL's source clock. During this
period, output will be masked '0'.
APLL_LOCK /
MPLL_LOCK /
EPLL_LOCK
RESERVED [31:16] RESERVED
PLL_LOCKTIME
PLL_CON register controls the operation of each PLL. If ENABLE bit is set, the corresponding PLL generates
output after PLL locking period. The output frequency of PLL is controlled by the MDIV, PDIV, SDIV, and KDIV
values. APLL_LOCK, MPLL_LOCK, and EPLL_LOCK fields denote the number of external clock. User can adjust
this fields which must be larger than 300us.
APLL_CON /
MPLL_CON
ENABLE
RESERVED [30:26] RESERVED
MDIV [25:16] PLL M divide value
RESERVED [15:14] RESERVED
PDIV
RESERVED
SDIV
The reset value of APLL_CON / MPLL_CON generate 400MHz and 133MHz output clock respectively, if the input
clock frequency is 12MHz.
ADDRSS R/W
0x7E00_F000 R/W
0x7E00_F004 R/W
0x7E00_F008 R/W
R/W
0x7E00_F010 R/W
0x7E00_F014 R/W
0x7E00_F018 R/W
BIT
[15:0] Required period to generate a stable clock output
BIT
[31] PLL enable control (0: disable, 1: enable)
[13:8] PLL P divide value
[7:3] RESERVED
[2:0] PLL S divide value
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DESCRIPTION
Control PLL locking period for APLL
Control PLL locking period for MPLL
Control PLL locking period for EPLL
Control PLL output frequency for APLL
Control PLL output frequency for MPLL
Control PLL output frequency for EPLL
Control PLL output frequency for EPLL
DESCRIPTION
DESCRIPTION
SYSTEM CONTROLLER
RESET VALUE
0x0000_FFFF
0x0000_FFFF
0x0000_FFFF
0x0190_0302
0x0214_0603
0x0020_0102
0x0000_9111
RESET VALUE
0x0000
0xFFFF
RESET VALUE
0
0x00
0x190 / 0x214
0x0
0x3 / 0x6
0x00
0x2 / 0x3
3-21