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TV ENCODER
TVENCREG2
Register
VBPORCH
0x76200004
VBPORCH
VEFBPD
VOFBPD
TVENCREG3
Register
HBPORCH
0x76200008
HBPORCH
HSPW
HBPD
TVENCREG4
Register
HEnhOffset
0x7620000C
HEnhOffset
VACTWinCenCTRL
HACTWinCenCTRL
DTOffset
HEOV
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
17-18
Specifications and information herein are subject to change without notice.
Address
R/W
R/W
Vertical back porch end point
Bit
[31:25]
Reserved
Vertical even field back porch end point
[24:16]
NTSC : 0x11C(284) , PAL : 0x14F(335)
[15:8]
Reserved
Vertical odd field back porch end point
[7:0]
NTSC : 0x15(21), PAL : 0x16(22)
Address
R/W
R/W
Horizontal back porch end point
Bit
[31:24]
Reserved
Horizontal sync pulse width
[23:16]
Default : 0x80(128) (NTSC, PAL)
[15:11]
Reserved
Horizontal back porch end point
[10:0]
NTSC : 0xF4(244), PAL : 0x108(264)
Address
R/W
R/W
Horizontal enhancer offset
Bit
[31:30]
Reserved
[29:24]
Vertical active window center control
[23:16]
Horizontal active window center contrl
[15:11]
Reserved
Data input timing offset value
[10:8]
NTSC, PAL : 0x4(4)
[7:5]
Reserved
Horizontal enhancer offset value. The enhancer
needs 26-cycles before TV encoder starts( 0 ~ 31)
[4:0]
Default : 0x1A(26) (NTSC, PAL)
S3C6400X RISC MICROPROCESSOR
Description
Description
Description
Description
Description
Description
Reset Value
0x011C0015
Reset Value
0
0x11C
0
0x15
Reset Value
0x008000F4
Reset Value
0
0x80
0
0xF4
Reset Value
0x0000041A
Reset Value
0
0
0
0
0x4
0
0x1A
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