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DISPLAY CONTROLLER
Window 4 Position Control B Register
Register
VIDOSD4B
VIDOSD4B
OSD_RightBotX_F
OSD_RightBotY_F
Note. Registers must have word boundary X position.
So, 24 BPP mode must have X position by 1 pixel. ( ex, X = 0,1,2,3....)
16 BPP mode must have X position by 2 pixel. ( ex, X = 0,2,4,6....)
8 BPP mode must have X position by 4 pixel. ( ex, X = 0,4,8,12....)
Window 4 Position Control C Register
Register
VIDOSD4C
VIDOSD4C
-
ALPHA0_R
ALPHA0_G
ALPHA0_B
ALPHA1_R
ALPHA1_G
ALPHA1_B
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
14-54
Specifications and information herein are subject to change without notice.
Address
R/W
0x77100084
R/W
Bit
[21:11]
Horizontal screen coordinate for right bottom pixel of OSD image
[10:0]
Vertical screen coordinate for right bottom pixel of OSD image
(for interlace TV output, this value MUST be set to half of the
original screen y coordinate. And the original screen y coordinate
MUST be odd value.)
Address
R/W
0x77100088
R/W
Bit
[24]
Reserved
[23:20]
Red Alpha value(case AEN == 0)
[19:16]
Green Alpha value(case AEN == 0)
[15:12]
Blue Alpha value(case AEN == 0)
[11:8]
Red Alpha value(case AEN == 1)
[7:4]
Green Alpha value(case AEN == 1)
[3:0]
Blue Alpha value(case AEN == 1)
Description
Video Window 4's position control register
Description
Description
Video Window 4's alpha control register
Description
S3C6400X RISC MICROPROCESSOR
Reset
Value
0x0
initial
state
0
0
Reset
Value
0x0
initial
state
0
0
0
0
0
0
0
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