Samsung S3C6400X User Manual page 1016

S3C6400 RISC MICROPROCESSOR
UART FIFO STATUS REGISTER
Register Address
UFSTAT0 0x7F005018
UFSTAT1 0x7F005418
UFSTAT2 0x7F005818
UFSTAT3 0x7F005C18
There are three UART FIFO status registers including UFSTAT0, UFSTAT1, UFSTAT2 and UFSTAT3 in the
UART block.
UFSTATn
Reserved
Tx FIFO Full
Tx FIFO Count
Reserved
Rx FIFO Full
Rx FIFO Count
R/W
R UART channel 0 FIFO status register
R UART channel 1 FIFO status register
R UART channel 2 FIFO status register
R UART channel 3 FIFO status register
Bit
[15]
[14] Set to 1 automatically whenever transmit FIFO is full
during transmit operation
0 = 0-byte ≤ Tx FIFO data ≤ 63-byte
1 = Full
[13:8] Number of data in Tx FIFO
[7]
[6] Set to 1 automatically whenever receive FIFO is full
during receive operation
0 = 0-byte ≤ Rx FIFO data ≤ 63-byte
1 = Full
[5:0] Number of data in Rx FIFO
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
UART
Reset Value
0x00
0x00
0x00
0x00
Initial State
0
0
0
0
0
0
31-21