Samsung S3C6400X User Manual page 584

S3C6400X RISC MICROPROCESSOR
GLOBAL CONTROL REGISTER
Register Address
CIGCTRL 0x78000008
CIGCTRL
SwRst
CamRst
reserved
TestPattern [28:27]
InvPolPCLK
InvPolVSYNC
InvPolHREF
reserved
IRQ_Ovfen
Href_mask
IRQ_LEVEL
IRQ_CLR_c
IRQ_CLR_p
Reserved [17:0]
R/W
RW
Bit
Camera interface software reset. Before setting this bit, you must
set the ITU601_656n bit of CISRCFMT as "1" temporarily at first
SFR setting. Next sequence is recommended.
(ITU601 case : ITU601_656n "1" → SwRst "1" → SwRst "0" for
[31]
first SFR setting ,
ITU656 case : ITU601_656n "1" → SwRst "1" → SwRst "0" →
ITU601_656n "0" for first SFR setting)
[30] External camera processor Reset or Power Down control
[29]
This register must be set at only ITU-T 601 8-bit mode. Not
allowed with input 16-bit mode or ITU-T 656 mode. (max. 1280 X
1024)
00 : external camera processor input (normal)
01 : color bar test pattern
10 : horizontal increment test pattern
11 . vertical increment test pattern
[26] 1 : inverse the polarity of PCLK
[25] 1 : inverse the polarity of VSYNC
[24] 1 : inverse the polarity of HREF
[23]
1 : Overflow interrupt enable (Interrupt is generated during
overflow occurrence)
[22]
0 : Overflow interrupt disable (normal)
1 : mask out Href during Vsync high
[21]
0 : no mask
1 : Level interrupt
0 : Edge trigger interrupt (default)
[20]
* This bit should be set to '1' because of using level interrupt
method in S3C6400x
This bit is related only to Level interrupt. Codec path interrupt is
[19]
cleared when IRQ_CLR_c is written to '1'. This bit Auto-clear.
This bit is related only to Level interrupt. Preview path interrupt is
[18]
cleared when IRQ_CLR_p is written to '1'. This bit Auto-clear.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Global control register
Description
0 : normal
0 : normal
0 : normal
CAMERA INTERFACE
Reset Value
2000_0000
Initial
M L
State
0
X X
0
X X
1
X X
0
X X
0
X X
0
X X
0
X X
0
X X
0
X X
0
X X
0
X X
0
X X
0
X X
20-19