Samsung S3C6400X User Manual page 588

S3C6400X RISC MICROPROCESSOR
CODEC OUTPUT CR1 START ADDRESS REGISTER
Register Address
CICOCRSA1 0x78000038
CICOCRSA1
CICOCRSA1 [31:0]
CODEC OUTPUT CR2 START ADDRESS REGISTER
Register Address
CICOCRSA2 0x7800003C
CICOCRSA2
CICOCRSA2 [31:0]
CODEC OUTPUT CR3 START ADDRESS REGISTER
Register Address
CICOCRSA3 0x78000040
CICOCRSA3
CICOCRSA3 [31:0]
CODEC OUTPUT CR4 START ADDRESS REGISTER
Register Address
CICOCRSA4 0x78000044
CICOCRSA4
CICOCRSA4 [31:0]
R/W
RW
Bit
st
Cr 1 frame start address for codec DMA
R/W
RW
Bit
nd
Cr 2 frame start address for codec DMA
R/W
RW
Bit
rd
Cr 3 frame start address for codec DMA
R/W
RW
Bit
th
Cr 4 frame start address for codec DMA
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
st
Cr 1 frame start address for codec DMA
Description
Description
nd
Cr 2 frame start address for codec DMA
Description
Description
rd
Cr 3 frame start address for codec DMA
Description
Description
th
Cr 4 frame start address for codec DMA
Description
CAMERA INTERFACE
Reset Value
0
Initial
M L
State
0
O X
Reset Value
0
Initial
M L
State
0
O X
Reset Value
0
Initial
M L
State
0
O X
Reset Value
0
Initial
M L
State
0
O X
20-23