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S3C6400 RISC MICROPROCESSOR
synchronization logic improves the DMA request response time.
If necessary, the DMA response signals, DMACCLR and DMACTC, must be synchronized in the peripheral.
Channel source address register, DMACCxSrcAddr
The eight read/write DMACCxSrcAddr registers contain the current source address (byte-aligned) of the data to be
transferred.
Each register is programmed directly by software before the appropriate channel is enabled. When the DMA
channel is enabled this register is updated:
As the source address is incremented
By following the linked list when a complete packet of data has been transferred.
Reading the register when the channel is active does not provide useful information. This is because by the time that
software has processed the value read, the channel might have progressed. It is intended to be read only when the
channel has stopped, in which case it shows the source address of the last item read.
Note: The source and destination addresses must be aligned to the source and destination widths.
Table 11-16 shows the bit assignment of the DMACCxSrcAddr registers.
DMACCxSrcAddr
SrcAddr
Channel destination address register, DMACCxDestAddr
The eight read/write DMACCxDestAddr registers contain the current destination address (byte-aligned) of the data
to be transferred.
Each register is programmed directly by software before the channel is enabled. When the DMA channel is enabled,
the register is updated as the destination address is incremented and by following the linked list when a complete
packet of data has been transferred.
Reading the register when the channel is active does not provide useful information. This is because by the time that
software has processed the value read, the channel might have progressed. It is intended to be read only when a
channel has stopped, in which case it shows the destination address of the last item read.
Table 11-17 shows the bit assignment of a DMACCxDestAddr register.
DMACCxDestAddr
DestAddr
Table 11-16. Bit Assignment of DMACCxSrcAddr register
Bits
Type
Function
[31:0]
R/W
DMA Source address
Table 11-17. Bit Assignment of DMACCxDestAddr register
Bits
Type
Function
[31:0]
R/W
DMA destination address
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DMA
11-21
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