Samsung S3C6400X User Manual page 1015

UART
UART ERROR STATUS REGISTER
Register Address
UERSTAT0 0x7F005014
UERSTAT1 0x7F005414
UERSTAT2 0x7F005814
UERSTAT3 0x7F005C14
There are three UART Rx error status registers including UERSTAT0, UERSTAT1, UERSTAT2 and UERSTAT3
in the UART block.
UERSTATn
Break Detect
Frame Error
Parity Error
Overrun Error
Note: These bits (UERSATn[3:0]) are automatically cleared to 0 when the UART error status register is read.
31-20
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
R/W
R UART channel 0 Rx error status register
R UART channel 1 Rx error status register
R UART channel 2 Rx error status register
R UART channel 3 Rx error status register
Bit
[3] Set to 1 automatically to indicate that a break signal has been
received.
0 = No break receive
1 = Break receive (Interrupt is requested.)
[2] Set to 1 automatically whenever a frame error occurs during
receive operation.
0 = No frame error during receive
1 = Frame error (Interrupt is requested.)
[1] Set to 1 automatically whenever a parity error occurs during
receive operation.
0 = No parity error during receive
1 = Parity error (Interrupt is requested.)
[0] Set to 1 automatically whenever an overrun error occurs during
receive operation.
0 = No overrun error during receive
1 = Overrun error (Interrupt is requested.)
S3C6400 RISC MICROPROCESSOR
Description
Description
Reset Value
0x0
0x0
0x0
0x0
Initial State
0
0
0
0