Samsung S3C6400X User Manual page 165

NAND FLASH CONTROLLER
NAND FLASH MEMORY TIMING
HCLK
CLE / ALE
nWE
DATA
Figure 8-3. CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) Block Diagram
Figure 8-4 nWE & nRE Timing (TWRPH0=0, TWRPH1=0) Block Diagram
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
8-4
Specifications and information herein are subject to change without notice.
TACLS
HCLK
nWE / nRE
DATA
TWRPH0 TWRPH1
COMMAND / ADDRESS
TWRPH0 TWRPH1
DATA
S3C6400X RISC MICROPROCESSOR