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S3C6400X RISC MICROPROCESSOR
Reserved
[0]
0: 4 address cycle
This bit is determined by OM[1] pin status during reset and wake-up
from sleep mode.
This bit can be changed by software.
Reserved. Must be written 0.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1: 5 address cycle
NAND FLASH CONTROLLER
0
8-15
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