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DMA
Interrupt status register, DMACIntStatus
The DMACIntStatus register is read-only and indicates the status of the interrupts after masking. A HIGH bit
indicates that a specific DMA channel interrupt request is active. The request can be generated from either the error
or terminal count interrupt requests.
Table 11-2 shows the bit assignment of the DMACIntStatus register.
DMACIntStatus
IntStatus
Interrupt terminal count status register, DMACIntTCStatus
The DMACIntTCStatus register is read-only and indicates the status of the terminal count after masking.
This register must be used in conjunction with the DMACIntStatus register if the combined interrupt request,
DMACINTCOMBINE, is used to request interrupts.
If the DMACINTTC interrupt request is used then you only have to read the DMACIntTCStatus register to ascertain
the source of the interrupt request.
Table 11-3 shows the bit assignment of the DMACIntTCStatus register.
DMACIntTCStatus
IntTCStatus
Interrupt terminal count clear register, DMACIntTCClear
The DMACIntTCClear register is write-only and is used to clear a terminal count interrupt request.
When writing to this register, each data bit that is set HIGH causes the corresponding bit in the status register to be
cleared. Data bits that are LOW have no effect on the corresponding bit in the register.
Table 11-4 shows the bit assignment of the DMACIntTCClear register.
DMACIntTCClear
IntTCClear
Preliminary product information describe products that are in development,
11-16
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Table 11-2. Bit Assignment of DMACIntStatus register
Bits
Type
Function
[7:0]
R
Status of the DMA interrupts after masking
Table 11-3. Bit Assignment of DMACIntTCStatus register
Bits
Type
Function
[7:0]
R
Interrupt terminal count request status
Table 11-4. Bit Assignment of DMACIntTCClear register
Bits
Type
Function
[7:0]
W
Terminal count request clear
S3C6400 RISC MICROPROCESSOR
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