Samsung S3C6400X User Manual page 959

S3C6400X RISC MICROPROCESSOR
Address = BASEADDR + 0x04 (0x7E00_6004)
Bits Name
[31:24] TxHOLD time
[23:16] TxIDLE time
[15:8] TxREQ time
[7] TxHOLD
time_en
[6] TxIDLE time_en
[5] TxREQ time_en
[4] Err_clr
[3:2] Width of CHID
[1] Burst_mode
[0] Frame_mode
INTSRC_REG
INTSRC_REG is interrupt source pending register.
Address = BASEADDR + 0x0C (0x7E00_600C)
Bits Name
[31:5] Reserved
[4] TxH_timeout
[3] TxI_timeout
[2] TxR_timeout
Description
TxHOLD state timer setting value
TxIDLE state timer setting value
TxREQ state timer setting value
TxHOLD state timer enabler
0 : disable
TxIDLE state timer enabler
0 : disable
TxREQ state timer enabler
0 : disable
Generated Error clear
0 : stay
Width of channel ID
Fixed channel ID mode
0 : Burst ch ID mode
Frame mode
0 : Stream mode
Table 28-7 CONFIG_REG register description
Description
Reserved bits
TxHOLD state timeout interrupt (set '1' for clearing)
TxIDLE state timeout interrupt (set '1' for clearing)
TxREQ state timeout interrupt (set '1' for clearing)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1 : enable
1 : enable
1 : enable
1 : clear
1 : Single ch ID mode
1 : Frame mode
MIPI HSI
R/W Reset Value
R/W 0xFF
R/W 0xFF
R/W 0xFF
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x1
R/W 0x0
R/W Reset Value
R 0x0000001
R/W 0x0
R/W 0x0
R/W 0x0
28-15