Samsung S3C6400X User Manual page 702

S3C6400X RISC MICROPROCESSOR
RET_DEC_SEQ_FRAME_DELAY (0x1D0)
Bit
4:0
RET_DEC_SEQ_INFO (0x1D4)
Bit
0
1
2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-76
Specifications and information herein are subject to change without notice.
Typ
Name
e
FrameBufDelay R
Name Type
DataPartEn R
RevVlcEn R
ShortVideoHeader R
Function
Maximum display frame buffer delay for buffering
decoded picture reorder.
BIT processor may delay decoded picture display for
display reordering when H.264, pic_order_cnt_type
"0" or "1" case or VC-1 decode case.
For example, BIT processor return [FrameBufDelay]
to "5". Then BIT processor returns after 5 picture
decoding at the first DEC_PIC_RUN command
because during first 5 frames, there is no decoded
picture to be displayed.
Maximum [FrameBufDelay] value may be 16.
This value is "0" if [ReorderEn] flag is "0" at H.264
case.
In VC-1 decode case, this value is "0" if there is no B
picture, "1" if there is a B picture regardless
[ReorderEn] flag.
In MPEG4/H.263 case, this value will be 0 (no delay)
Function
0 – Data Partition Disable
1 – Data Partition Enable
After executing completion of decode
DEC_SEQ_INIT command, BIT write to this
register with data partition enable flag from
decoded sequence header information.
In encode case, this register is not used.
0 – Normal VLC table used
1 – Reversible VLC table used
This bit is ignored if DataPartEn bit is '0'
0 – Normal MPEG4 Stream
1 – Short Video Header Stream
MULTI-FORMAT VIDEO CODEC
Command
DEC_SEQ_I
NIT
Comman
d
DEC_SEQ_
INIT