Samsung S3C6400X User Manual page 829

USB2.0 HS OTG
GUSBCFG
[31:16]
PHY Low-Power
Clock Select
[14:10]
HNPCap
SRPCap
PHYIf
TOutCal
CORE RESET REGISTER (GRSTCTL)
The application uses this register to reset various hardware features inside the core.
Register Address
GRSTCTL 0x7C00_0010
GRSTCTL
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-22
Specifications and information herein are subject to change without notice.
Bit R/W
Reserved
[15] PHY Low-Power Clock Select
Selects either 480-MHz or 48-MHz (low-power) PHY
mode. In FS and LS modes, the PHY can usually
operate on a 48-MHz clock to save power.
· 1'b0 : 480-MHz Internal PLL clock
· 1'b1 : 48-MHz External clock
*Note : This bit must be configured with
OPHYPWR.pll_powerdown.
Reserved
R_W
[9] HNP – Capable
The application uses this bit to control the OTG
cores's HNP capabilities.
·1'b0 : HNP capability is not enabled
·1'b1 : HNP capability is enabled
R_W
[8] SRP – Capable
The application uses this bit to control the OTG
core's SRP capabilities.
· 1'b0 : SRP capability is not enabled
· 1'b1 : SRP capability is enabled
[7:4] Reserved
[3] R_W PHY Interface
The application uses this bit to configure the core to
support a UTMI+ PHY with an 8- or 16-bit interface.
Only 16-bit interface is supported. This bit must be
set to 1.
· 1'b0 : 8 bits
· 1'b1 : 16 bits
[2:0] R_W HS/FS Timeout Calibration
Set this bit to 3'h7.
R/W
R/W
Bit R/W
S3C6400X RISC MICROPROCESSOR
Description
Description
Core Reset Register
Description
Initial State
16'h0
1'b0
4'h5
1'b0
1'b0
4'h0
1'b0
3'h0
Reset Value
32 bits
Initial State