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SYSTEM CONTROLLER
Clock generation for audio (IIS and PCM)
Figure 3-11 generates special clocks for audio interface logics, which include IIS and PCM. S3C6400X has two
IIS channels and two PCM channels, supports only two channels at any given time. Usually, EPLL generates one
special clock for an audio interface. If S3C6400X requires two independent clock frequency, i.e., there is no
integer relationship between two audio interfaces, the remaining clock can be supplied directly through external
oscillators or using MPLL.
EXTCLK
1
XTIpll
0
MPLL
IISCDCLK0
IISCDCLK1
EPLL
PCMCDCLK
Clock generation for UART, SPI, and MMC
Figure 3-12 shows the clock generator for UART, SPI and MMC. There is one additional clock source, CLK27M,
to give more flexibility.
EXTCLK
1
XTIpll
0
MPLL
EPLL
CLK27M
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-10
Specifications and information herein are subject to change without notice.
MUX
MPLL
0
1
DIV
MPLL
CLK_SRC[1]
CLK_DIV0[4]
MUX
0
EPLL
1
CLK_SRC[2]
Figure 3-11. Audio clock generation
MUX
0
MPLL
1
DIV
MPLL
CLK_SRC[1]
CLK_DIV0[4]
0
MUX
EPLL
1
CLK_SRC[2]
Figure 3-12. UART/SPI/MMC clock generation
S3C6400X RISC MICROPROCESSOR
MUX
AUDIO0
0
1
2
DIV
AUDIO0
3
4
CLK_SRC[9:7]
CLK_DIV2[11:8]
MUX
AUDIO1
0
1
2
DIV
AUDIO1
3
4
CLK_SRC[12:10]
CLK_DIV2[15:12]
MUX
UART
0
DIV
UART
1
CLK_SRC[13]
CLK_DIV2[19:16]
0
MUX
SPI0,1
1
0
DIV
1
2
SPI0
DIV
3 2
SPI1
3
CLK_SRC[15:14]
CLK_SRC[17:16]
CLK_DIV2[3:0]
CLK_DIV2[7:4]
0
MUX
MMC
1
0
DIV
1
0
2
MMC0
DIV
1
3 2
MMC1
DIV
3
2
MMC2
3
CLK_SRC[19:18]
CLK_SRC[21:20]
SCLK_GATE[25]
CLK_SRC[23:22]
CLK_DIV1[3:0]
CLK_DIV1[7:4]
SCLK_GATE[8]
SCLK_GATE[9]
SCLK_GATE[9]
SCLK_GATE[20]
SCLK_GATE[21]
SCLK_GATE[24]
SCLK_GATE[26]
CLK_DIV1[11:8]
CLKAUDIO0
CLKAUDIO1
CLKUART
CLKSPI0
CLKSPI1
CLKMMC0
CLKMMC1
CLKMMC2
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