Samsung S3C6400X User Manual page 1014

S3C6400 RISC MICROPROCESSOR
UART TX/RX STATUS REGISTER
Register Address
UTRSTAT0 0x7F005010
UTRSTAT1 0x7F005410
UTRSTAT2 0x7F005810
UTRSTAT3 0x7F005C10
There are three UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1, UTRSTAT2 and UTRSTAT3 in
the UART block.
UTRSTATn
Transmitter empty
Transmit buffer empty
Receive buffer data ready
R/W
R UART channel 0 Tx/Rx status register
R UART channel 1 Tx/Rx status register
R UART channel 2 Tx/Rx status register
R UART channel 3 Tx/Rx status register
Bit
[2] Set to 1 automatically when the transmit buffer register has
no valid data to transmit and the transmit shift register is
empty.
0 = Not empty
1 = Transmitter (transmit buffer & shifter register) empty
[1] Set to 1 automatically when transmit buffer register is empty.
0 =The buffer register is not empty
1 = Empty
(In Non-FIFO mode, Interrupt or DMA is requested.
In FIFO mode, Interrupt or DMA is requested, when Tx
FIFO Trigger Level is set to 00 (Empty))
If the UART uses the FIFO, you must check Tx FIFO Count
bits and Tx FIFO Full bit in the UFSTAT register instead of
this bit.
[0] Set to 1 automatically whenever receive buffer register
contains valid data, received over the RXDn port.
0 = Empty
1 = The buffer register has a received data
(In Non-FIFO mode, Interrupt or DMA is requested)
If the UART uses the FIFO, you must check Rx FIFO Count
bits and Rx FIFO Full bit in the UFSTAT register instead of
this bit.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
UART
Reset Value
0x6
0x6
0x6
0x6
Initial State
1
1
0
31-19