Samsung S3C6400X User Manual page 929

S3C6400X RISC MICROPROCESSOR
NORMAL INTERRUPT STATUS ENABLE REGISTER
Setting to 1 enables Interrupt Status.
Register
NORINTSTSEN0 0x7C200034
NORINTSTSEN1 0x7C300034
NORINTSTSEN2 0x7C400034
Name Bit
[15]
[14]
EnStaFIA3
[13]
EnStaFIA2
[12]
EnStaFIA1
[11]
EnStaFIA0
[10]
EnStaRWait
[9]
EnStaCCS
[8]
[7]
[6]
Address R/W
R/W
R/W
R/W
Fixed to 0
The Host Driver shall control error interrupts using the Error Interrupt
Status Enable register. (RO)
FIFO SD Address Pointer Interrupt 3 Status Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 2 Status Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 1 Status Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 0 Status Enable
'1' = Enabled
'0' = Masked
Read Wait interrupt status enable
'1' = Enabled
'0' = Masked
CCS Interrupt Status Enable
'1' = Enabled
'0' = Masked
Card Interrupt Status Enable
If this bit is set to 0, the Host Controller clears interrupt request to the
System. The Card Interrupt detection is stopped when this bit is
cleared and restarted when this bit is set to 1. The Host Driver must
clear the Card Interrupt Status Enable before servicing the Card
Interrupt and must set this bit again after all interrupt requests from the
card are cleared to prevent inadvertent interrupts.
'1' = Enabled
'0' = Masked
Card Removal Status Enable
'1' = Enabled
'0' = Masked
Card Insertion Status Enable
'1' = Enabled
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Normal Interrupt Status Enable Register
(Channel 0)
Normal Interrupt Status Enable Register
(Channel 1)
Normal Interrupt Status Enable Register
(Channel 2)
Description
HSMMC CONTROLLER
Reset Value
0x0
0x0
0x0
Initial Value
0
0
0
0
0
0
0
0
0
0
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