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Pulse Width Modulation Timer
TIMER INTERRUPT GENERATION
The PWMTIMER provides flexibility to generate Pulse and Level Interrupts by controlling the 'INTRGEN_SEL'
port status. When the port 'INTRGEN_SEL' is tied to logic 1, optional level interrupts will be generated or
optional pulse interrupts will be generated. The interrupt generation is controlled by writing specific values to the
'TINT_CSTAT' register within PWMTIMER. Interrupt generation is optional based on programmed value in
'TINT_CSTAT' register.
PROGRAMMER'S MODEL
OVERVIEW
For controlling and observing the status of PWM, following registers can be used:
1.
TCFG0: Clock-Prescalar and Dead-Zone Configurations
2.
TCFG1: Clock Multiplexers and DMA Mode Select
3.
TCON: Timer Control Register
4.
TCNTB0: Timer 0 Count Buffer Register
5.
TCMPB0: Timer 0 Compare Buffer Register
6.
TCNTO0: Timer 0 Count Observation Register
7.
TCNTB1: Timer 1 Count Buffer Register
8.
TCMPB1: Timer 1 Compare Buffer Register
9.
TCNTO1: Timer 1 Count Observation Register
10. TCNTB2: Timer 2 Count Buffer Register
11. TCMPB2: Timer 2 Compare Buffer Register
12. TCNTO2: Timer 2 Count Observation Register
13. TCNTB3: Timer 3 Count Buffer Register
14. TCMPB3: Timer 3 Compare Buffer Register
15. TCNTO3: Timer 3 Count Observation Register
16. TCNTB4: Timer 4 Count Buffer Register
17. TCNTO4: Timer 4 Count Observation Register
18. TINT_CSTAT:Timer Interrupt Control and Status Register
32-14
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
S3C6400 RISC MICROPROCESSOR
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