Samsung S3C6400X User Manual page 614

S3C6400X RISC MICROPROCESSOR
MSCOCBOFF
Reserved [31:24]
MSCOCBOFF [23:0]
MSDMA FOR CODEC CR OFFSET REGISTER
Register Address
MSCOCROFF 0x780000F4
MSCOCROFF
Reserved [31:24]
MSCOCROFF [23:0]
MSDMA FOR CODEC SOURCE IMAGE WIDTH REGISTER
Register Address
MSCOWIDTH 0x780000F8
MSCOWIDTH
AutoLoadEnable
ADDR_CH_DIS
Reserved [29:28]
MSCOHEIGHT [27:16]
Reserved [15:12]
MSCOWIDTH [11:0]
Bit
Offset of Cb component for fetching source image(non-interleave
YCbCr 4:2:0, 4:2:2)
R/W
RW
Bit
Offset of Cr component for fetching source image(non-interleave
YCbCr 4:2:0, 4:2:2)
R/W
RW
Bit
MSDMA Automatically restart (Only Software trigger mode)
At the first frame start requires ENVID start setting. After first
[31]
frame, next frame does not need ENVID setting.
0 : AutoLoad Disable , 1 : AutoLoad Enable
MSDMA Address Change Disable (Only Software trigger mode)
[30] At the first frame start needs ADDR_CH_DIS = '0'
0 : Address change enable , 1 : Address change disable
MSDMA source image vertical pixel size. minimum 8. It must be
multiple of PreVerRatio.
MSDMA source image horizontal pixel size (must be 8's multiple.
It must be 4's multiple of PreHorRatio. minimum 16)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
MSDMA Cr offset related
Description
Description
MSDMA source image width related
Description
CAMERA INTERFACE
Initial
M L
State
0
X X
0
O X
Reset Value
0000_0000
Initial
M L
State
0
X X
0
O X
Reset Value
0000_0000
Initial
M L
State
0
O X
0
O X
0
X X
0
O X
0
X X
0
O X
20-49