Table of Contents
Advertisement
S3C6400X RISC MICROPROCESSOR
Command Setting Example)
** CMD0_EN = 2'b10, CMD1_EN = 2'b11, CMD2_EN = 2'b01, CMD3_EN = 2'b11, CMD4_EN = 2'b01
(Auto Command : CMD0, CMD1, CMD3,
** AUTO_COMMAND_RATE = 4'b0010 (per 4 frames)
** CMD0_RS = 1, CMD1_RS = 1, CMD2_RS = 0, CMD3_RS = 1, CMD4_RS = 0
** RSPOL = 0
1. Auto Command
VD[17:0]
F(n)
RS
2. Normal Command
VD[17:0]
ENVIDS
NORMAL_CMD_START (SFR)
RS
I80 CPU Interface Trigger
VTIME_I80 starts its operation only when a S/W trigger occurs. There are two kinds of triggers.
S/W trigger is generated by setting SW_CPUSTTRIG SFR.
Interrupt
Frame Done Interrupt is generated at the completion of one frame.
Normal Command : CMD1, CMD2, CMD3, CMD4)
C0
F(n+1)
F(n+2)
F(n+3)
C1
C2
C3
C4
F(n)
auto clear
Figure 14-6. Sending Command
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
C1 C3
F(n+4)
F(n+5)
F(n+6)
...
F(n+1)
DISPLAY CONTROLLER
F(n+7)
F(n+8)
C0 C1 C3
F(m)
C1
C2
C3
C4
pending
auto clear
F(n+9)
F(m+1)
14-27
Advertisement
Table of Contents
