Samsung S3C6400X User Manual page 1019

UART
UART BAUD RATE CONFIGURE REGISTER
There are four UART baud rate divisor registers including UBRDIV0, UBRDIV1, UBRDIV2 and UBRDIV3 in the
UART block.
The value stored in the baud rate divisor register (UBRDIVn) and dividing slot register(UDIVSLOTn), are used to
determine the serial Tx/Rx clock rate (baud rate) as follows:
DIV_VAL = UBRDIVn + (num of 1's in UDIVSLOTn)/16
DIV_VAL = (PCLK / (bps x 16 ) ) –1
DIV_VAL = (EXT_UCLK0 / (bps x 16 ) ) –1
or
DIV_VAL = (EXT_UCLK1 / (bps x 16 ) ) –1
Where, the divisor must be from 1 to (2
Using UDIVSLOT, you can make more accurate baud rate.
For example, if the baud-rate is 115200 bps and PCLK ,EXT_UCLK0 or EXT_UCLK1 is 40 MHz, UBRDIVn and
UDIVSLOTn are:
DIV_VAL
UBRDIVn = 20 ( integer part of DIV_VAL )
(num of 1's in UDIVSLOTn)/16 = 0.7
then, (num of 1's in UDIVSLOTn) = 11
so, UDIVSLOTn can be 16'b1110_1110_1110_1010 or 16'b0111_0111_0111_0101, etc.
We recommend selecting UDIVSLOTn as described in the following table:
Num of 1's
0 0x0000(0000_0000_0000_0000b)
1 0x0080(0000_0000_0000_1000b)
2 0x0808(0000_1000_0000_1000b)
3 0x0888(0000_1000_1000_1000b)
4 0x2222(0010_0010_0010_0010b)
5 0x4924(0100_1001_0010_0100b)
6 0x4A52(0100_1010_0101_0010b)
7 0x54AA(0101_0100_1010_1010b)
31-24
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
16
-1)
= (40000000 / (115200 x 16) ) -1
= 21.7 -1
= 20.7
UDIVSLOTn
S3C6400 RISC MICROPROCESSOR
Num of 1's
8 0x5555(0101_0101_0101_0101b)
9 0xD555(1101_0101_0101_0101b)
10 0xD5D5(1101_0101_1101_0101b)
11 0xDDD5(1101_1101_1101_0101b)
12 0xDDDD(1101_1101_1101_1101b)
13 0xDFDD(1101_1111_1101_1101b)
14 0xDFDF(1101_1111_1101_1111b)
15 0xFFDF(1111_1111_1101_1111b)
UDIVSLOTn