Samsung S3C6400X User Manual page 965

S3C6400X RISC MICROPROCESSOR
Address = BASEADDR + 0x08
Bits Name
[31] RxFIFO_clr
[30:28] Reserved
[27] RxFIFO_timer_e
n
[26:24] Reserved
[23:0] RxFIFO_time
INTSRC_REG
INTSRC_REG is interrupt source panding register.
Address = BASEADDR + 0x0C
Bits Name
[31:8] Reserved
[7] Break_done
[6] Added_clock
[5] Missed_clock
[4] RxACK_timeout
[3] Brframe_err
[2] RxDONE
[1] RxFIFO_timeout
[0] RxFIFO_full
Description
Break frame receiving timer setting value
Reserved bits
RxFIFO timer enabler
Reserved bits
RxFIFO timer setting value
Table 28-15 CONFIG1_REG register description
Description
Reserved bits
Received Break frame in Frame mode
(set '1' for clearing)
Added clock input (set '1' for clearing)
Missed clock input interrupt (set '1' for clearing)
RxACK state timeout interrupt (set '1' for clearing)
Received data is not break frame.
(set '1' for clearing)
Data receiving is Done.
(set '1' for clearing)
RxFIFO timeout but RxFIFO is not empty.
(set '1' for clearing)
RxFIFO full interrupt (set '1' for clearing)
Table 28-16 INTSRC_REG register description
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MIPI HSI
R/W Reset Value
R/W 0x0
R 0x0
R/W 0x0
R 0x0
R/W 0xFFFFFF
R/W Reset Value
R 0x000000
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
28-21