Samsung S3C6400X User Manual page 187

NAND FLASH CONTROLLER
SPARE AREA ECC STATUS REGISTER
Register Address
NFSECC 0x7020003C
NFSECC
Reserved
SECC0_1
SECC0_0
Note: The NAND flash controller generate NFSECC when read or write spare area data while the
SpareECCLock(NFCONT[6]) bit is '0'(Unlock).
MLC 4-BIT ECC ERROR PATTEN REGISTER
Register Address
NFMLCBITPT 0x70200040
NFMLCBITPT
th
4 Error bit pattern
rd
3 Error bit pattern
nd
2 Error bit pattern
st
1 Error bit pattern
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
8-26
Specifications and information herein are subject to change without notice.
R/W
R NAND Flash ECC register for I/O [7:0]
Bit
[31:16] Reserved
[15:8] Spare area ECC1 Status for I/O[7:0]
[7:0] Spare area ECC0 Status for I/O[7:0]
R/W
R NAND Flash 4-bit ECC Error Pattern register for data[7:0]
Bit
th
[31:24] 4 Error bit pattern
rd
[23:16] 3 Error bit pattern
nd
[15:8] 2 Error bit pattern
st
[7:0] 1 Error bit pattern
S3C6400X RISC MICROPROCESSOR
Description
Description
Description
Description
Reset Value
0xXXXXXX
Initial State
0xXXXX
0xXX
0xXX
Reset Value
0x00000000
Initial State
0x00
0x00
0x00
0x00