Samsung S3C6400X User Manual page 803

HOST INTERFACE
CPUIF Interrupt Enable Mirrored Register (CPUIFC_MR_INTE)
Offset=0x30, R/W, Reset Value=0x0000_2000
Field
Reserved
INTE
CPUIF Interrupt Enable1 Mirrored Register (CPUIFC_MR_INTE1)
Offset=0x34, R/W, Reset Value=0x0000_0000
Field
Reserved
INTE1
CPUIF Interrupt Enable2 Register (CPUIFC_INTE2)
Offset=0x38, R/W, Reset Value=0x0000_0000
Field
Reserved
INTE2
24-26
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Bit
[31:16]
[15:0] Mirrored Protocol Register of INTE[15:0]
Bit
[31:16]
[15:0] Mirrored Protocol Register of INTE1[15:0]
Bit
[31:16]
[15:0] Each bit is an interrupt enable control bit of the
corresponding bit of CPUIF_STAT2
S3C6400X
Description
Description
Description
RISC MICROPROCESSOR
Initial State
0x0000
0x2000
Initial State
0x0000
0x0000
Initial State
0x0000
0x0000