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S3C6400X RISC MICROPROCESSOR
CLOCK ARCHITECTURE
Figure 3-2 shows the block diagram of the clock generation module. The clock source selects between an
external crystal (XXTIpll) and external clock (XEXTCLK). The clock generator consists of three PLL's (Phase
Locked Loop) which generate high frequency clock signals up to 1.4GHz.
Figure 3-2. The block diagram of clock generator
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SYSTEM CONTROLLER
3-3
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