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S3C6400X RISC MICROPROCESSOR
HSMMC CONTROLLER
Figure 27-3. Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer
Figure 27-4. Timing of Command Inhibit (DAT) for the case of response with busy
Figure 27-5. Timing of Command Inhibit (CMD) for the case of no response command
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-37
Specifications and information herein are subject to change without notice.
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