Samsung S3C6400X User Manual page 846

S3C6400X RISC MICROPROCESSOR
HAINT
[31:16]
HAINT
HOST ALL CHANNELS INTERRUPT MASK REGISTER (HAINTMSK)
The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the
application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of
16 bits.
· Mask interrupt : 1'b0
· Unmask interrupt : 1'b0
Register Address
HAINTMSK 0x7C00_0418
HAINTMSK
[31:16]
HAINTMsk
HOST PORT CONTROL AND STATUS REGISTERS
HOST PORT CONTROL AND STATUS REGISTER (HPRT)
This register is available in both Host and Device modes. Currently, the OTG Host supports only one port. A
single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status,
connect status, and test mode for each port. The R_SS_WC bits in this register can trigger an interrupt to the
application through the Host Port Interrupt bit of the Core Interrupt register. On a Port Interrupt, the application
must read this register and clear the bit that caused the interrupt. For the R_SS_WC bits, the application must
write a 1 to the bit to clear the interrupt.
Register Address
HPRT 0x7C00_0440
HPRT
[31:19]
PrtSpd [18:17]
Bit R/W
Reserved
[15:0] RO Channel Interrupts
One bit per channel : Bit 0 for Channel 0, bit 15 for
Channel 15
R/W
R/W
Bit R/W
Reserved
[15:0] R_W Channel Interrupt Mask
One bit per channel : Bit 0 for Channel 0, bit 15 for
Channel 15
R/W
R/W
Bit R/W
Reserved
RO Port Speed
Indicates the speed of the device attached to this
port.
· 2'b00 : High speed
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Host All Channels Interrupt Mask Register
Description
Description
Host Port Control and Status Register
Description
USB2.0 HS OTG
Initial State
16'h0
16'h0
Reset Value
32 bits
Initial State
16'h0
16'h0
Reset Value
32 bits
Initial State
13'h0
2'b0
26-39