Samsung S3C6400X User Manual page 865

Table of Contents

Advertisement

USB2.0 HS OTG
Register
Address
DOEPCTL0
0x7C00_0B00
DOEPCTL0
EPEna
EPDis
[29:28]
SetNAK
CNAK
[25:22]
Stall
Snp
EPType
[19:18]
NAKsts
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-58
Specifications and information herein are subject to change without notice.
R/W
R/W
Device Control OUT Endpoint 0 Control Register
Bit
R/W
[31]
R_WS_
Endpoint Enable
SC
Indicates that the application has allocated the
memory to start receiving data from the USB. The
core clears this bit before setting any of the following
interrupts on this endpoint.
· SETUP Phase Done
· Endpoint Disabled
· Transfer Complete
Note : In DMA mode, this bit must be set for the core
to transfer SETUP data packets into memory.
[30]
RO
Endpoint Disable
The application cannot disable control OUT endpoint
0.
Reserved
[27]
WO
Set NAK
A write to this bit sets the NAK bit for the endpoint.
Using this bit, the application can control the
transmission of NAK handshakes on an endpoint.
The core can also set this bit on a Transfer
Completed interrupt, or after a SETUP is received on
the endpoint.
[26]
WO
Clear NAK
A write to this bit clears the NAK bit for the endpoint.
Reserved
[21]
R_WS_
STALL Handshake
SC
The application can only set this bit, and the core
clears it, when a SETUP token is received for this
endpoint. If a NAK bit or Global OUT NAK is set
along with this bit, the STALL bit takes priority.
Irrespective of this bit's setting, the core always
responds to SETUP data packets with an ACK
handshake.
[20]
R_W
Snoop Mode
This bit configures the endpoint to Snoop mode. In
Snoop mode, the core does not check the
correctness of OUT packets before transferring them
to application memory.
RO
Endpoint Type
Hardcoded to 2'b00 for control.
[17]
RO
NAK Status
Indicates the following:
S3C6400X RISC MICROPROCESSOR
Description
Description
Reset Value
32 bits
Initial State
1'b0
1'b0
2'b0
1'b0
1'b0
4'h0
1'b0
1'b0
2'h0
1'b0

Advertisement

Table of Contents
loading

Table of Contents