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DISPLAY CONTROLLER
LCD I80 CPU INTERFACE
Signals
Name
SYS_VDIN[17:0]
SYS_VDOUT[17:0]
SYS_CS0
SYS_CS1
SYS_WE
SYS_OE
SYS_RS
Note: LCD_SEL[1:0] value @ 0x7F0081A0 must be set as '00' to use Host I/F Style. Please, refer to GPIO
Manual for more information.
Timing
VCLK
RS
nCS
nWE
DATA
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
14-30
Specifications and information herein are subject to change without notice.
Table 14-6. I80 CPU Interface Pin Description
Type
Source/Destination
In
Video Mux
Out
Video Mux
Output
Video Mux
Output
Video Mux
Output
Video Mux
Output
Video Mux
Output
Video Mux
LCD_CS_SETUP
LCD_WR _SETUP
Figure 14-9. I80 CPU system interface WRITE Cycle Timing
S3C6400X RISC MICROPROCESSOR
Description
Video Data Input
Video Data Output
Chip select for LCD0
Chip select for LCD1
Write enable
Output Enable
Register/State Select
LCD_WR_ACT
LCD_WR_HOLD
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