Samsung S3C6400X User Manual page 183

NAND FLASH CONTROLLER
NFCON STATUS REGISTER
Register Address
NFSTAT 0x70200028 R/W NAND Flash operation status register
NFSTAT
Reserved [31:24]
BootDone
Reserved
ECCDecDone
IllegalAccess
RnB_TransDetect
NCE[1]
(Read-only)
NCE[0]
(Read-only)
Reserved
RnB
(Read-only)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
8-22
Specifications and information herein are subject to change without notice.
R/W
Bit
Read undefined
[23]
When NAND Flash is set as booting device, it indicates whether
loading boot area to Stepping stone is finished or not.
[22:7]
Reserved
[6] When 4-bit ECC decoding is finished, this value set and issue
interrupt if enabled. The NFMLCBITPT, NFMLCL0 and
NFMLCEL1 have valid values., .To clear this write to '1'
1: 4-bit ECC decoding is completed
[5]
Once Soft Lock or Lock-tight is enabled, The illegal access
(program, erase) to the memory makes this bit set.
0: illegal access is not detected
1: illegal access is detected
[4] When RnB low to high transition is occurred, this value set and
issue interrupt if enabled. To clear this write '1'.
0: RnB transition is not detected
1: RnB transition is detected
Transition configuration is set in RnB_TransMode(NFCONT[8]).
[3]
The status of nCE[1] output pin
[2]
The status of nCE[0] output pin
[1]
Reserved
[0] The status of RnB input pin.
0: NAND Flash memory busy
1: NAND Flash memory ready to operate
S3C6400X RISC MICROPROCESSOR
Description
Description
Reset Value
0x0080001D
Initial State
0x00
1
0x00
0
0
1
1
1
0
1