Samsung S3C6400X User Manual page 893

S3C6400X RISC MICROPROCESSOR
Note: When writing to the upper byte of the Command register, the SD command is issued and DMA is started.
(7) Wait for the Command Complete Interrupt.
(8) Write 1 to the Command Complete in the Normal Interrupt Status register to clear this bit.
(9) Read Response register and get necessary information in accordance with the issued command.
(10) Wait for the Transfer Complete Interrupt and DMA Interrupt.
(11) If Transfer Complete is set 1, go to Step (14) else if DMA Interrupt is set to 1; proceed to Step (12). Transfer
Complete is higher priority than DMA Interrupt.
(12) Write 1 to the DMA Interrupt in the Normal Interrupt Status register to clear this bit.
(13) Set the next system address of the next data position to the System Address register and go to Step (10).
(14) Write 1 to the Transfer Complete and DMA Interrupt in the Normal Interrupt Status register to clear this bit.
Note: Step (2) and Step (3) can be executed simultaneously. Step (5) and Step (6) can also be
executed simultaneously.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
HSMMC CONTROLLER
27-17