Samsung S3C6400X User Manual page 169

NAND FLASH CONTROLLER
ECC MODULE FEATURES
ECC generation is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit of the Control register.
When ECCLock is Low, ECC codes are generated by the H/W ECC modules.
SLC ECC Register Configuration
Following tables shows the configuration of SLC ECC value read from spare area of external NAND flash
memory. For comparing to ECC parity code generated by the H/W modules, the format of ECC read from
memory is important.
NOTE: MLC ECC decoding scheme is different to SLC ECC.
1) 8-bit NAND Flash Memory Interface
Register
NFMECCD0 4
NFMECCD1
Register
NFSECCD
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
8-8
Specifications and information herein are subject to change without notice.
Bit [31:24]
th rd
ECC for I/O[7:0] 3
Bit [31:24]
Not used
Bit [23:16]
nd
ECC for I/O[7:0] 2 ECC for I/O[7:0]
Not used
Bit [23:16]
nd
2 ECC for I/O[7:0]
S3C6400X RISC MICROPROCESSOR
Bit [15:8]
st
1 ECC for I/O[7:0]
Bit [15:8]
st
1 ECC for I/O[7:0]
Bit [7:0]
Bit [7:0]