Samsung S3C6400X User Manual page 118

DRAM CONTROLLER
PnT_RP Bit
[31:6]
scheduled_RP [5:3]
t_RP [2:0]
T_RRD REGISTER
Register
P0T_RRD 0x7E000034
P1T_RRD 0x7E001034
PnT_RRD Bit
[31:4]
t_RRD [3:0]
T_WR REGISTER
Register
P0T_WR 0x7E000038
P1T_WR 0x7E001038
PnT_WR Bit
[31:3]
t_WR [2:0]
T_WTR REGISTER
Register
P0T_WTR 0x7E00003C
P1T_WTR 0x7E00103C
PnT_WTR Bit
[31:3]
t_WTR [2:0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
5-12
Specifications and information herein are subject to change without notice.
Read undefined. Write as Zero
Set the precharge to RAS delay in aclk cycles -3.
Set the precharge to RAS delay in memory clock cycles
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set Active bank x to Active bank y delay in memory clock cycles.
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set the write to precharge delay in memory clock cycles.
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set the write to read delay in memory clock cycles.
Description
Description
16-bit DRAM controller t_RRD register
32-bit DRAM controller t_RRD register
Description
Description
16-bit DRAM controller t_WR register
32-bit DRAM controller t_WR register
Description
Description
16-bit DRAM controller t_WTR register
32-bit DRAM controller t_WTR register
Description
S3C6400X RISC MICROPROCESSOR
Initial State
Reset Value
Initial State
Reset Value
Initial State
Reset Value
Initial State
011
101
0x2
0x2
0x2
0x3
0x3
011
0x2
0x2
010