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FIMV-MFC V1.0
RunCodStd (0x16C)
Bit
2:0
IntEnable (0x170)
Bit
15:0
Name
Type
CodStd
R/W
Host writes the codec standard index code to this
register before every writing run command
3'b000 : MPEG4/H.263 DECODER
3'b001 : MPEG4/H.263 ENCODER
3'b010 : H.264 DECODER
3'b011 : H.264 ENCODER
3'b100 : VC-1 DECODER
Name
Type
IntEnable
R/W
Interrupt Enable Flag register.
Each bit of this register is interrupt enable flag of
various interrupt. "1" means interrupt enable so BIT
generates interrupt and "0" means interrupt disable
0th bit (LSB) : Initialize complete. This interrupt is
generated at once after BIT run
1st bit : SEQ_INIT command execution complete
2nd bit: SEQ_END command execution complete
3rd bit : PIC_RUN command execution complete
4th bit: SET_FRAME_BUF command complete
5th bit: ENC_HEADER command complete
6th bit: ENC_PARA_SET command complete
7th bit: DEC_PARA_SET command complete
8th ~ 13th bits: Reserved
14th bit: External bit stream buffer is empty status in
decoding case
15th bit: External bit stream buffer is full status in
encoding case
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MULTI-FORMAT
Function
Function
CODEC
VIDEO
Reset
Value
N/A
Reset
Value
N/A
21-69
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